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From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v5 3/5] drm/i915: Introduce for_each_dbuf_slice_in_mask macro
Date: Tue,  7 Apr 2020 13:32:20 +0300	[thread overview]
Message-ID: <20200407103222.15629-4-stanislav.lisovskiy@intel.com> (raw)
In-Reply-To: <20200407103222.15629-1-stanislav.lisovskiy@intel.com>

We quite often need now to iterate only particular dbuf slices
in mask, whether they are active or related to particular crtc.

v2: - Minor code refactoring
v3: - Use enum for max slices instead of macro

Let's make our life a bit easier and use a macro for that.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.h       | 7 +++++++
 drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index cc7f287804d7..9aab7e5181fd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -187,6 +187,13 @@ enum plane_id {
 	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 		for_each_if((__crtc)->plane_ids_mask & BIT(__p))
 
+#define for_each_dbuf_slice_in_mask(__slice, __mask) \
+	for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
+		for_each_if((BIT(__slice)) & (__mask))
+
+#define for_each_dbuf_slice(__slice) \
+	for_each_dbuf_slice_in_mask(__slice, BIT(I915_MAX_DBUF_SLICES) - 1)
+
 enum port {
 	PORT_NONE = -1,
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index da64a5edae7a..b682fd3d0973 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -311,6 +311,7 @@ intel_display_power_put_async(struct drm_i915_private *i915,
 enum dbuf_slice {
 	DBUF_S1,
 	DBUF_S2,
+	I915_MAX_DBUF_SLICES
 };
 
 #define with_intel_display_power(i915, domain, wf) \
-- 
2.24.1.485.gad05a3d8e5

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  parent reply	other threads:[~2020-04-07 10:36 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-07 10:32 [Intel-gfx] [PATCH v5 0/5] Consider DBuf bandwidth when calculating CDCLK Stanislav Lisovskiy
2020-04-07 10:32 ` [Intel-gfx] [PATCH v5 1/5] drm/i915: Decouple cdclk calculation from modeset checks Stanislav Lisovskiy
2020-04-07 10:32 ` [Intel-gfx] [PATCH v5 2/5] drm/i915: Force recalculate min_cdclk if planes config changed Stanislav Lisovskiy
2020-04-07 10:32 ` Stanislav Lisovskiy [this message]
2020-04-07 10:32 ` [Intel-gfx] [PATCH v5 4/5] drm/i915: Adjust CDCLK accordingly to our DBuf bw needs Stanislav Lisovskiy
2020-04-07 10:32 ` [Intel-gfx] [PATCH v5 5/5] drm/i915: Remove unneeded hack now for CDCLK Stanislav Lisovskiy
2020-04-07 13:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Consider DBuf bandwidth when calculating CDCLK (rev8) Patchwork
2020-04-07 13:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-07 19:51 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-04-07 20:29   ` Lisovskiy, Stanislav
2020-04-07 20:46     ` Vudum, Lakshminarayana
2020-04-08  8:03       ` Lisovskiy, Stanislav
2020-04-07 20:58 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork

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