From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v5 5/5] drm/i915: Remove unneeded hack now for CDCLK
Date: Tue, 7 Apr 2020 13:32:22 +0300 [thread overview]
Message-ID: <20200407103222.15629-6-stanislav.lisovskiy@intel.com> (raw)
In-Reply-To: <20200407103222.15629-1-stanislav.lisovskiy@intel.com>
No need to bump up CDCLK now, as it is now correctly
calculated, accounting for DBuf BW as BSpec says.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index fbb8cbcee3d2..b8c41cd4452e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2069,18 +2069,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/* Account for additional needs from the planes */
min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
- /*
- * HACK. Currently for TGL platforms we calculate
- * min_cdclk initially based on pixel_rate divided
- * by 2, accounting for also plane requirements,
- * however in some cases the lowest possible CDCLK
- * doesn't work and causing the underruns.
- * Explicitly stating here that this seems to be currently
- * rather a Hack, than final solution.
- */
- if (IS_TIGERLAKE(dev_priv))
- min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
-
if (min_cdclk > dev_priv->max_cdclk_freq) {
drm_dbg_kms(&dev_priv->drm,
"required cdclk (%d kHz) exceeds max (%d kHz)\n",
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-04-07 10:36 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-07 10:32 [Intel-gfx] [PATCH v5 0/5] Consider DBuf bandwidth when calculating CDCLK Stanislav Lisovskiy
2020-04-07 10:32 ` [Intel-gfx] [PATCH v5 1/5] drm/i915: Decouple cdclk calculation from modeset checks Stanislav Lisovskiy
2020-04-07 10:32 ` [Intel-gfx] [PATCH v5 2/5] drm/i915: Force recalculate min_cdclk if planes config changed Stanislav Lisovskiy
2020-04-07 10:32 ` [Intel-gfx] [PATCH v5 3/5] drm/i915: Introduce for_each_dbuf_slice_in_mask macro Stanislav Lisovskiy
2020-04-07 10:32 ` [Intel-gfx] [PATCH v5 4/5] drm/i915: Adjust CDCLK accordingly to our DBuf bw needs Stanislav Lisovskiy
2020-04-07 10:32 ` Stanislav Lisovskiy [this message]
2020-04-07 13:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Consider DBuf bandwidth when calculating CDCLK (rev8) Patchwork
2020-04-07 13:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-07 19:51 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-04-07 20:29 ` Lisovskiy, Stanislav
2020-04-07 20:46 ` Vudum, Lakshminarayana
2020-04-08 8:03 ` Lisovskiy, Stanislav
2020-04-07 20:58 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200407103222.15629-6-stanislav.lisovskiy@intel.com \
--to=stanislav.lisovskiy@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox