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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: chris@chris-wilson.co.uk
Subject: [Intel-gfx] [PATCH 1/4] drm/i915: Setup multicast register steering for all gen >= 10
Date: Thu, 30 Apr 2020 16:15:26 -0700	[thread overview]
Message-ID: <20200430231529.295556-2-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20200430231529.295556-1-matthew.d.roper@intel.com>

Steering of multicast registers for workarounds is needed on all
platforms gen10 and above.  Move the wa_init_mcr() call to the
higher-level gt_init_workarounds() rather than re-calling it for each
individual platform.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index adddc5c93b48..4a255de13394 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -870,8 +870,6 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 static void
 cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
-	wa_init_mcr(i915, wal);
-
 	/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
 	if (IS_CNL_REVID(i915, CNL_REVID_B0, CNL_REVID_B0))
 		wa_write_or(wal,
@@ -887,8 +885,6 @@ cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 static void
 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
-	wa_init_mcr(i915, wal);
-
 	/* WaInPlaceDecompressionHang:icl */
 	wa_write_or(wal,
 		    GEN9_GAMT_ECO_REG_RW_IA,
@@ -943,8 +939,6 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 static void
 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
-	wa_init_mcr(i915, wal);
-
 	/* Wa_1409420604:tgl */
 	if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
 		wa_write_or(wal,
@@ -961,6 +955,9 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 static void
 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
+	if (INTEL_GEN(i915) >= 10)
+		wa_init_mcr(i915, wal);
+
 	if (IS_GEN(i915, 12))
 		tgl_gt_workarounds_init(i915, wal);
 	else if (IS_GEN(i915, 11))
-- 
2.24.1

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  reply	other threads:[~2020-04-30 23:15 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-30 23:15 [Intel-gfx] [PATCH 0/4] Steer multicast register workaround verification Matt Roper
2020-04-30 23:15 ` Matt Roper [this message]
2020-04-30 23:15 ` [Intel-gfx] [PATCH 2/4] drm/i915: Steer multicast register readback in wa_verify Matt Roper
2020-04-30 23:15 ` [Intel-gfx] [PATCH 3/4] drm/i915: Don't skip verification of MCR engine workarounds Matt Roper
2020-04-30 23:15 ` [Intel-gfx] [PATCH 4/4] drm/i915: Add MCR ranges for gen11 and gen12 Matt Roper
2020-05-01  0:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Steer multicast register workaround verification Patchwork
2020-05-01  0:21 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-05-01  8:01 ` [Intel-gfx] [PATCH 0/4] " Tvrtko Ursulin
2020-05-01 16:05   ` Matt Roper

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