From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v8 5/7] drm/i915: Introduce for_each_dbuf_slice_in_mask macro
Date: Thu, 14 May 2020 18:21:43 +0300 [thread overview]
Message-ID: <20200514152145.2449-6-stanislav.lisovskiy@intel.com> (raw)
In-Reply-To: <20200514152145.2449-1-stanislav.lisovskiy@intel.com>
We quite often need now to iterate only particular dbuf slices
in mask, whether they are active or related to particular crtc.
v2: - Minor code refactoring
v3: - Use enum for max slices instead of macro
Let's make our life a bit easier and use a macro for that.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.h | 7 +++++++
drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index efb4da205ea2..b7a6d56bac5f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -187,6 +187,13 @@ enum plane_id {
for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
for_each_if((__crtc)->plane_ids_mask & BIT(__p))
+#define for_each_dbuf_slice_in_mask(__slice, __mask) \
+ for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
+ for_each_if((BIT(__slice)) & (__mask))
+
+#define for_each_dbuf_slice(__slice) \
+ for_each_dbuf_slice_in_mask(__slice, BIT(I915_MAX_DBUF_SLICES) - 1)
+
enum port {
PORT_NONE = -1,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 6c917699293b..4d0d6f9dad26 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -314,6 +314,7 @@ intel_display_power_put_async(struct drm_i915_private *i915,
enum dbuf_slice {
DBUF_S1,
DBUF_S2,
+ I915_MAX_DBUF_SLICES
};
#define with_intel_display_power(i915, domain, wf) \
--
2.24.1.485.gad05a3d8e5
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next prev parent reply other threads:[~2020-05-14 15:26 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-14 15:21 [Intel-gfx] [PATCH v8 0/7] Consider DBuf bandwidth when calculating CDCLK Stanislav Lisovskiy
2020-05-14 15:21 ` [Intel-gfx] [PATCH v8 1/7] drm/i915: Decouple cdclk calculation from modeset checks Stanislav Lisovskiy
2020-05-14 15:21 ` [Intel-gfx] [PATCH v8 2/7] drm/i915: Extract cdclk requirements checking to separate function Stanislav Lisovskiy
2020-05-14 19:36 ` Manasi Navare
2020-05-14 15:21 ` [Intel-gfx] [PATCH v8 3/7] drm/i915: Check plane configuration properly Stanislav Lisovskiy
2020-05-14 19:38 ` Manasi Navare
2020-05-14 15:21 ` [Intel-gfx] [PATCH v8 4/7] drm/i915: Plane configuration affects CDCLK in Gen11+ Stanislav Lisovskiy
2020-05-14 19:41 ` Manasi Navare
2020-05-14 15:21 ` Stanislav Lisovskiy [this message]
2020-05-14 19:57 ` [Intel-gfx] [PATCH v8 5/7] drm/i915: Introduce for_each_dbuf_slice_in_mask macro Manasi Navare
2020-05-14 15:21 ` [Intel-gfx] [PATCH v8 6/7] drm/i915: Adjust CDCLK accordingly to our DBuf bw needs Stanislav Lisovskiy
2020-05-14 15:43 ` Stanislav Lisovskiy
2020-05-14 20:15 ` Manasi Navare
2020-05-14 18:26 ` kbuild test robot
2020-05-16 21:49 ` kbuild test robot
2020-05-14 15:21 ` [Intel-gfx] [PATCH v8 7/7] drm/i915: Remove unneeded hack now for CDCLK Stanislav Lisovskiy
2020-05-15 15:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Consider DBuf bandwidth when calculating CDCLK (rev13) Patchwork
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