From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 09/15] drm/i915/rkl: Don't try to access transcoder D
Date: Thu, 4 Jun 2020 19:55:29 +0300 [thread overview]
Message-ID: <20200604165529.GW6112@intel.com> (raw)
In-Reply-To: <20200603211529.3005059-10-matthew.d.roper@intel.com>
On Wed, Jun 03, 2020 at 02:15:23PM -0700, Matt Roper wrote:
> There are a couple places in our driver that loop over transcoders A..D
> for gen11+; since RKL only has three pipes/transcoders, this can lead to
> unclaimed register reads/writes. We should add checks for transcoder
> existence where appropriate.
>
> v2: Move one transcoder check that wound up in the wrong function after
> conflict resolution. It belongs in bdw_get_trans_port_sync_config
> rather than bxt_get_dsi_transcoder_state.
>
> v3: Switch loops to use for_each_cpu_transcoder_masked() since this
> iterator already checks the platform's transcoder mask for us.
> (Ville)
>
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f3ea81a17352..40a71c4a1ef5 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2885,13 +2885,15 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> enum pipe pipe;
> + u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
>
> intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
>
> if (INTEL_GEN(dev_priv) >= 12) {
> enum transcoder trans;
>
> - for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
> + for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
> enum intel_display_power_domain domain;
>
> domain = POWER_DOMAIN_TRANSCODER(trans);
> @@ -3413,6 +3415,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
> u32 de_port_enables;
> u32 de_misc_masked = GEN8_DE_EDP_PSR;
> + u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
> enum pipe pipe;
>
> if (INTEL_GEN(dev_priv) <= 10)
> @@ -3433,7 +3437,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> if (INTEL_GEN(dev_priv) >= 12) {
> enum transcoder trans;
>
> - for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
> + for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
> enum intel_display_power_domain domain;
>
> domain = POWER_DOMAIN_TRANSCODER(trans);
> --
> 2.24.1
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2020-06-04 16:55 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-03 21:15 [Intel-gfx] [PATCH v3 00/15] Remaining RKL patches Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 01/15] drm/i915/rkl: Set transcoder mask properly Matt Roper
2020-06-04 15:34 ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 Matt Roper
2020-06-03 22:34 ` Aditya Swarup
2020-06-03 23:12 ` Matt Roper
2020-06-04 1:18 ` Aditya Swarup
2020-06-04 17:01 ` Ville Syrjälä
2020-06-04 22:12 ` Matt Roper
2020-06-05 11:43 ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 03/15] drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2} Matt Roper
2020-06-04 18:31 ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 04/15] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 05/15] drm/i915/rkl: Setup ports/phys Matt Roper
2020-06-04 17:09 ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 06/15] drm/i915/rkl: provide port/phy mapping for vbt Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 07/15] drm/i915/rkl: Update TGP's pin mapping when paired with RKL Matt Roper
2020-06-04 18:29 ` Ville Syrjälä
2020-06-04 23:18 ` Matt Roper
2020-06-05 11:52 ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 08/15] drm/i915/rkl: Add DDC pin mapping Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 09/15] drm/i915/rkl: Don't try to access transcoder D Matt Roper
2020-06-04 16:55 ` Ville Syrjälä [this message]
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 10/15] drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper
2020-06-04 16:59 ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 11/15] drm/i915/rkl: Handle comp master/slave relationships for PHYs Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 12/15] drm/i915/rkl: Add DPLL4 support Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 13/15] drm/i915/rkl: Handle HTI Matt Roper
2020-06-04 16:59 ` Ville Syrjälä
2020-06-04 22:55 ` Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 14/15] drm/i915/rkl: Disable PSR2 Matt Roper
2020-06-04 17:41 ` Rodrigo Vivi
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 15/15] drm/i915/rkl: Add initial workarounds Matt Roper
2020-06-03 22:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Remaining RKL patches Patchwork
2020-06-03 22:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-03 22:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-04 8:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-06-04 16:39 ` Matt Roper
2020-06-05 22:11 ` Chris Wilson
2020-06-06 3:21 ` Matt Roper
2020-06-06 9:01 ` Chris Wilson
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