From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
Date: Thu, 4 Jun 2020 20:01:57 +0300 [thread overview]
Message-ID: <20200604170157.GZ6112@intel.com> (raw)
In-Reply-To: <20200603211529.3005059-3-matthew.d.roper@intel.com>
On Wed, Jun 03, 2020 at 02:15:16PM -0700, Matt Roper wrote:
> RKL uses the same BW_BUDDY programming table as TGL, but programs the
> values into a single set BUDDY0 set of registers rather than the
> BUDDY1/BUDDY2 sets used by TGL.
Maybe we just want some kind of HAS_ABOX() so we could use the same
thing here and in the ABOX_CTL programming?
>
> Bspec: 49218
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 44 +++++++++++--------
> drivers/gpu/drm/i915/i915_reg.h | 14 ++++--
> 2 files changed, 35 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 72312b67b57a..2c1ce50b572b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> enum intel_dram_type type = dev_priv->dram_info.type;
> u8 num_channels = dev_priv->dram_info.num_channels;
> const struct buddy_page_mask *table;
> - int i;
> + int config, min_buddy, max_buddy, i;
>
> if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> /* Wa_1409767108: tgl */
> @@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> else
> table = tgl_buddy_page_masks;
>
> - for (i = 0; table[i].page_mask != 0; i++)
> - if (table[i].num_channels == num_channels &&
> - table[i].type == type)
> + if (IS_ROCKETLAKE(dev_priv)) {
> + min_buddy = max_buddy = 0;
> + } else {
> + min_buddy = 1;
> + max_buddy = 2;
> + }
> +
> + for (config = 0; table[config].page_mask != 0; config++)
> + if (table[config].num_channels == num_channels &&
> + table[config].type == type)
> break;
>
> - if (table[i].page_mask == 0) {
> + if (table[config].page_mask == 0) {
> drm_dbg(&dev_priv->drm,
> "Unknown memory configuration; disabling address buddy logic.\n");
> - intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
> - intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
> + for (i = min_buddy; i <= max_buddy; i++)
> + intel_de_write(dev_priv, BW_BUDDY_CTL(i),
> + BW_BUDDY_DISABLE);
> } else {
> - intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK,
> - table[i].page_mask);
> - intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK,
> - table[i].page_mask);
> -
> - /* Wa_22010178259:tgl */
> - intel_de_rmw(dev_priv, BW_BUDDY1_CTL,
> - BW_BUDDY_TLB_REQ_TIMER_MASK,
> - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
> - intel_de_rmw(dev_priv, BW_BUDDY2_CTL,
> - BW_BUDDY_TLB_REQ_TIMER_MASK,
> - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8));
> + for (i = min_buddy; i <= max_buddy; i++) {
> + intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i),
> + table[config].page_mask);
> +
> + /* Wa_22010178259:tgl,rkl */
> + intel_de_rmw(dev_priv, BW_BUDDY_CTL(i),
> + BW_BUDDY_TLB_REQ_TIMER_MASK,
> + REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK,
> + 0x8));
> + }
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 578cfe11cbb9..3e79cefc510a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7837,13 +7837,19 @@ enum {
> #define WAIT_FOR_PCH_RESET_ACK (1 << 1)
> #define WAIT_FOR_PCH_FLR_ACK (1 << 0)
>
> -#define BW_BUDDY1_CTL _MMIO(0x45140)
> -#define BW_BUDDY2_CTL _MMIO(0x45150)
> +#define _BW_BUDDY0_CTL 0x45130
> +#define _BW_BUDDY1_CTL 0x45140
> +#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
> + _BW_BUDDY0_CTL, \
> + _BW_BUDDY1_CTL))
> #define BW_BUDDY_DISABLE REG_BIT(31)
> #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
>
> -#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144)
> -#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154)
> +#define _BW_BUDDY0_PAGE_MASK 0x45134
> +#define _BW_BUDDY1_PAGE_MASK 0x45144
> +#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
> + _BW_BUDDY0_PAGE_MASK, \
> + _BW_BUDDY1_PAGE_MASK))
>
> #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
> #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4)
> --
> 2.24.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
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next prev parent reply other threads:[~2020-06-04 17:02 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-03 21:15 [Intel-gfx] [PATCH v3 00/15] Remaining RKL patches Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 01/15] drm/i915/rkl: Set transcoder mask properly Matt Roper
2020-06-04 15:34 ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 Matt Roper
2020-06-03 22:34 ` Aditya Swarup
2020-06-03 23:12 ` Matt Roper
2020-06-04 1:18 ` Aditya Swarup
2020-06-04 17:01 ` Ville Syrjälä [this message]
2020-06-04 22:12 ` Matt Roper
2020-06-05 11:43 ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 03/15] drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2} Matt Roper
2020-06-04 18:31 ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 04/15] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 05/15] drm/i915/rkl: Setup ports/phys Matt Roper
2020-06-04 17:09 ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 06/15] drm/i915/rkl: provide port/phy mapping for vbt Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 07/15] drm/i915/rkl: Update TGP's pin mapping when paired with RKL Matt Roper
2020-06-04 18:29 ` Ville Syrjälä
2020-06-04 23:18 ` Matt Roper
2020-06-05 11:52 ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 08/15] drm/i915/rkl: Add DDC pin mapping Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 09/15] drm/i915/rkl: Don't try to access transcoder D Matt Roper
2020-06-04 16:55 ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 10/15] drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper
2020-06-04 16:59 ` Ville Syrjälä
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 11/15] drm/i915/rkl: Handle comp master/slave relationships for PHYs Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 12/15] drm/i915/rkl: Add DPLL4 support Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 13/15] drm/i915/rkl: Handle HTI Matt Roper
2020-06-04 16:59 ` Ville Syrjälä
2020-06-04 22:55 ` Matt Roper
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 14/15] drm/i915/rkl: Disable PSR2 Matt Roper
2020-06-04 17:41 ` Rodrigo Vivi
2020-06-03 21:15 ` [Intel-gfx] [PATCH v3 15/15] drm/i915/rkl: Add initial workarounds Matt Roper
2020-06-03 22:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Remaining RKL patches Patchwork
2020-06-03 22:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-03 22:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-04 8:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-06-04 16:39 ` Matt Roper
2020-06-05 22:11 ` Chris Wilson
2020-06-06 3:21 ` Matt Roper
2020-06-06 9:01 ` Chris Wilson
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