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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v4 3/7] drm/i915/rkl: Update TGP's pin mapping when paired with RKL
Date: Tue, 9 Jun 2020 18:14:34 +0300	[thread overview]
Message-ID: <20200609151433.GR6112@intel.com> (raw)
In-Reply-To: <20200606025740.3308880-4-matthew.d.roper@intel.com>

On Fri, Jun 05, 2020 at 07:57:36PM -0700, Matt Roper wrote:
> HPD pin handling for RKL+TGP is a special case; we effectively select
> the HPD pin based on the DDI (A,B,D,E) rather than the PHY (A,B,C,D).
> This differs from the regular behavior of RKL+CMP (and also TGL+TGP).
> 
> v2:
>  - Rather than providing a custom hpd_pin mapping table, just assign
>    encoder->hpd_pin in a custom manner for this setup.  (Ville)
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_hotplug.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index 4f6f560e093e..d794dd5f170c 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -89,6 +89,15 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
>  {
>  	enum phy phy = intel_port_to_phy(dev_priv, port);
>  
> +	/*
> +	 * RKL + TGP PCH is a special case; we effectively choose the hpd_pin
> +	 * based on the DDI rather than the PHY (i.e., the last two outputs
> +	 * shold be HPD_PORT_{D,E} rather than {C,D}.  Note that this differs
> +	 * from the behavior of both TGL+TGP and RKL+CMP.
> +	 */
> +	if (IS_ROCKETLAKE(dev_priv) && HAS_PCH_TGP(dev_priv))
> +		return HPD_PORT_A + port - PORT_A;
> +
>  	switch (phy) {
>  	case PHY_F:
>  		return IS_CNL_WITH_PORT_F(dev_priv) ? HPD_PORT_E : HPD_PORT_F;
> -- 
> 2.24.1

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2020-06-09 15:14 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-06  2:57 [Intel-gfx] [PATCH v4 0/7] Remaining RKL patches Matt Roper
2020-06-06  2:57 ` [Intel-gfx] [PATCH v4 1/7] drm/i915/rkl: RKL uses ABOX0 for pixel transfers Matt Roper
2020-06-09 15:14   ` Ville Syrjälä
2020-06-06  2:57 ` [Intel-gfx] [PATCH v4 2/7] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Matt Roper
2020-06-06  2:57 ` [Intel-gfx] [PATCH v4 3/7] drm/i915/rkl: Update TGP's pin mapping when paired with RKL Matt Roper
2020-06-09 15:14   ` Ville Syrjälä [this message]
2020-06-06  2:57 ` [Intel-gfx] [PATCH v4 4/7] drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper
2020-06-09 15:15   ` Ville Syrjälä
2020-06-06  2:57 ` [Intel-gfx] [PATCH v4 5/7] drm/i915/rkl: Add DPLL4 support Matt Roper
2020-06-06  2:57 ` [Intel-gfx] [PATCH v4 6/7] drm/i915/rkl: Handle HTI Matt Roper
2020-06-06  2:57 ` [Intel-gfx] [PATCH v4 7/7] drm/i915/rkl: Add initial workarounds Matt Roper
2020-06-06  3:12 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Remaining RKL patches (rev2) Patchwork
2020-06-06  3:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-06  4:31 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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