* [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+
@ 2020-06-16 16:34 Matt Atwood
2020-06-16 16:39 ` Ville Syrjälä
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: Matt Atwood @ 2020-06-16 16:34 UTC (permalink / raw)
To: intel-gfx, aditya.swarup
Add minimum width to planes, variable with specific formats, for gen11+.
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 55 +++++++++++++++++---
1 file changed, 47 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7457813ef273..d4fdad6cb3b1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3760,6 +3760,45 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb,
}
}
+static int icl_min_plane_width(struct drm_i915_private *dev_priv,
+ const struct drm_framebuffer *fb)
+{
+ /* Wa_14011264657, Wa_14011050563 */
+ switch (fb->format->format) {
+ case DRM_FORMAT_C8:
+ return 18;
+ case DRM_FORMAT_RGB565:
+ return 10;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_XVYU2101010:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
+ return 6;
+ case DRM_FORMAT_NV12:
+ return 20;
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
+ return 12;
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ case DRM_FORMAT_XVYU12_16161616:
+ case DRM_FORMAT_XVYU16161616:
+ return 4;
+ default:
+ return 1;
+ }
+}
+
static int icl_max_plane_width(const struct drm_framebuffer *fb,
int color_plane,
unsigned int rotation)
@@ -3831,15 +3870,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
int y = plane_state->uapi.src.y1 >> 16;
int w = drm_rect_width(&plane_state->uapi.src) >> 16;
int h = drm_rect_height(&plane_state->uapi.src) >> 16;
- int max_width;
- int max_height;
- u32 alignment;
- u32 offset;
+ int max_width, min_width = 1, max_height;
+ u32 alignment, offset;
int aux_plane = intel_main_to_aux_plane(fb, 0);
u32 aux_offset = plane_state->color_plane[aux_plane].offset;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 11) {
max_width = icl_max_plane_width(fb, 0, rotation);
+ min_width = icl_min_plane_width(dev_priv, fb);
+ }
else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
max_width = glk_max_plane_width(fb, 0, rotation);
else
@@ -3850,10 +3889,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
else
max_height = skl_max_plane_height();
- if (w > max_width || h > max_height) {
+ if (w > max_width || w < min_width || h > max_height) {
drm_dbg_kms(&dev_priv->drm,
- "requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
- w, h, max_width, max_height);
+ "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
+ w, h, min_width, max_width, max_height);
return -EINVAL;
}
--
2.21.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+
2020-06-16 16:34 [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+ Matt Atwood
@ 2020-06-16 16:39 ` Ville Syrjälä
2020-06-16 17:01 ` Matt Atwood
2020-06-16 17:34 ` Ville Syrjälä
` (3 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Ville Syrjälä @ 2020-06-16 16:39 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
On Tue, Jun 16, 2020 at 09:34:06AM -0700, Matt Atwood wrote:
> Add minimum width to planes, variable with specific formats, for gen11+.
How did this suddenly become gen11+? Wasn't it rkl only before?
>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 55 +++++++++++++++++---
> 1 file changed, 47 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7457813ef273..d4fdad6cb3b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3760,6 +3760,45 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb,
> }
> }
>
> +static int icl_min_plane_width(struct drm_i915_private *dev_priv,
> + const struct drm_framebuffer *fb)
> +{
> + /* Wa_14011264657, Wa_14011050563 */
> + switch (fb->format->format) {
> + case DRM_FORMAT_C8:
> + return 18;
> + case DRM_FORMAT_RGB565:
> + return 10;
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_ABGR8888:
> + case DRM_FORMAT_XRGB2101010:
> + case DRM_FORMAT_XBGR2101010:
> + case DRM_FORMAT_ARGB2101010:
> + case DRM_FORMAT_ABGR2101010:
> + case DRM_FORMAT_XVYU2101010:
> + case DRM_FORMAT_Y212:
> + case DRM_FORMAT_Y216:
> + return 6;
> + case DRM_FORMAT_NV12:
> + return 20;
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> + return 12;
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> + case DRM_FORMAT_XVYU12_16161616:
> + case DRM_FORMAT_XVYU16161616:
> + return 4;
> + default:
> + return 1;
> + }
> +}
> +
> static int icl_max_plane_width(const struct drm_framebuffer *fb,
> int color_plane,
> unsigned int rotation)
> @@ -3831,15 +3870,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> int y = plane_state->uapi.src.y1 >> 16;
> int w = drm_rect_width(&plane_state->uapi.src) >> 16;
> int h = drm_rect_height(&plane_state->uapi.src) >> 16;
> - int max_width;
> - int max_height;
> - u32 alignment;
> - u32 offset;
> + int max_width, min_width = 1, max_height;
> + u32 alignment, offset;
> int aux_plane = intel_main_to_aux_plane(fb, 0);
> u32 aux_offset = plane_state->color_plane[aux_plane].offset;
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (INTEL_GEN(dev_priv) >= 11) {
> max_width = icl_max_plane_width(fb, 0, rotation);
> + min_width = icl_min_plane_width(dev_priv, fb);
> + }
> else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> max_width = glk_max_plane_width(fb, 0, rotation);
> else
> @@ -3850,10 +3889,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> else
> max_height = skl_max_plane_height();
>
> - if (w > max_width || h > max_height) {
> + if (w > max_width || w < min_width || h > max_height) {
> drm_dbg_kms(&dev_priv->drm,
> - "requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
> - w, h, max_width, max_height);
> + "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
> + w, h, min_width, max_width, max_height);
> return -EINVAL;
> }
>
> --
> 2.21.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+
2020-06-16 16:39 ` Ville Syrjälä
@ 2020-06-16 17:01 ` Matt Atwood
2020-06-16 17:06 ` Ville Syrjälä
0 siblings, 1 reply; 12+ messages in thread
From: Matt Atwood @ 2020-06-16 17:01 UTC (permalink / raw)
To: Ville Syrjälä, intel-gfx
On Tue, Jun 16, 2020 at 07:39:09PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 16, 2020 at 09:34:06AM -0700, Matt Atwood wrote:
> > Add minimum width to planes, variable with specific formats, for gen11+.
>
> How did this suddenly become gen11+? Wasn't it rkl only before?
gen11 platforms were currently in pending, that has changed.
>
> >
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 55 +++++++++++++++++---
> > 1 file changed, 47 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 7457813ef273..d4fdad6cb3b1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -3760,6 +3760,45 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb,
> > }
> > }
> >
> > +static int icl_min_plane_width(struct drm_i915_private *dev_priv,
> > + const struct drm_framebuffer *fb)
> > +{
> > + /* Wa_14011264657, Wa_14011050563 */
> > + switch (fb->format->format) {
> > + case DRM_FORMAT_C8:
> > + return 18;
> > + case DRM_FORMAT_RGB565:
> > + return 10;
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_ARGB8888:
> > + case DRM_FORMAT_ABGR8888:
> > + case DRM_FORMAT_XRGB2101010:
> > + case DRM_FORMAT_XBGR2101010:
> > + case DRM_FORMAT_ARGB2101010:
> > + case DRM_FORMAT_ABGR2101010:
> > + case DRM_FORMAT_XVYU2101010:
> > + case DRM_FORMAT_Y212:
> > + case DRM_FORMAT_Y216:
> > + return 6;
> > + case DRM_FORMAT_NV12:
> > + return 20;
> > + case DRM_FORMAT_P010:
> > + case DRM_FORMAT_P012:
> > + case DRM_FORMAT_P016:
> > + return 12;
> > + case DRM_FORMAT_XRGB16161616F:
> > + case DRM_FORMAT_XBGR16161616F:
> > + case DRM_FORMAT_ARGB16161616F:
> > + case DRM_FORMAT_ABGR16161616F:
> > + case DRM_FORMAT_XVYU12_16161616:
> > + case DRM_FORMAT_XVYU16161616:
> > + return 4;
> > + default:
> > + return 1;
> > + }
> > +}
> > +
> > static int icl_max_plane_width(const struct drm_framebuffer *fb,
> > int color_plane,
> > unsigned int rotation)
> > @@ -3831,15 +3870,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> > int y = plane_state->uapi.src.y1 >> 16;
> > int w = drm_rect_width(&plane_state->uapi.src) >> 16;
> > int h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > - int max_width;
> > - int max_height;
> > - u32 alignment;
> > - u32 offset;
> > + int max_width, min_width = 1, max_height;
> > + u32 alignment, offset;
> > int aux_plane = intel_main_to_aux_plane(fb, 0);
> > u32 aux_offset = plane_state->color_plane[aux_plane].offset;
> >
> > - if (INTEL_GEN(dev_priv) >= 11)
> > + if (INTEL_GEN(dev_priv) >= 11) {
> > max_width = icl_max_plane_width(fb, 0, rotation);
> > + min_width = icl_min_plane_width(dev_priv, fb);
> > + }
> > else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > max_width = glk_max_plane_width(fb, 0, rotation);
> > else
> > @@ -3850,10 +3889,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> > else
> > max_height = skl_max_plane_height();
> >
> > - if (w > max_width || h > max_height) {
> > + if (w > max_width || w < min_width || h > max_height) {
> > drm_dbg_kms(&dev_priv->drm,
> > - "requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
> > - w, h, max_width, max_height);
> > + "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
> > + w, h, min_width, max_width, max_height);
> > return -EINVAL;
> > }
> >
> > --
> > 2.21.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+
2020-06-16 17:01 ` Matt Atwood
@ 2020-06-16 17:06 ` Ville Syrjälä
0 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2020-06-16 17:06 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
On Tue, Jun 16, 2020 at 10:01:40AM -0700, Matt Atwood wrote:
> On Tue, Jun 16, 2020 at 07:39:09PM +0300, Ville Syrjälä wrote:
> > On Tue, Jun 16, 2020 at 09:34:06AM -0700, Matt Atwood wrote:
> > > Add minimum width to planes, variable with specific formats, for gen11+.
> >
> > How did this suddenly become gen11+? Wasn't it rkl only before?
> gen11 platforms were currently in pending, that has changed.
What does "in pending" mean?
> >
> > >
> > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 55 +++++++++++++++++---
> > > 1 file changed, 47 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 7457813ef273..d4fdad6cb3b1 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -3760,6 +3760,45 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb,
> > > }
> > > }
> > >
> > > +static int icl_min_plane_width(struct drm_i915_private *dev_priv,
> > > + const struct drm_framebuffer *fb)
> > > +{
> > > + /* Wa_14011264657, Wa_14011050563 */
> > > + switch (fb->format->format) {
> > > + case DRM_FORMAT_C8:
> > > + return 18;
> > > + case DRM_FORMAT_RGB565:
> > > + return 10;
> > > + case DRM_FORMAT_XRGB8888:
> > > + case DRM_FORMAT_XBGR8888:
> > > + case DRM_FORMAT_ARGB8888:
> > > + case DRM_FORMAT_ABGR8888:
> > > + case DRM_FORMAT_XRGB2101010:
> > > + case DRM_FORMAT_XBGR2101010:
> > > + case DRM_FORMAT_ARGB2101010:
> > > + case DRM_FORMAT_ABGR2101010:
> > > + case DRM_FORMAT_XVYU2101010:
> > > + case DRM_FORMAT_Y212:
> > > + case DRM_FORMAT_Y216:
> > > + return 6;
> > > + case DRM_FORMAT_NV12:
> > > + return 20;
> > > + case DRM_FORMAT_P010:
> > > + case DRM_FORMAT_P012:
> > > + case DRM_FORMAT_P016:
> > > + return 12;
> > > + case DRM_FORMAT_XRGB16161616F:
> > > + case DRM_FORMAT_XBGR16161616F:
> > > + case DRM_FORMAT_ARGB16161616F:
> > > + case DRM_FORMAT_ABGR16161616F:
> > > + case DRM_FORMAT_XVYU12_16161616:
> > > + case DRM_FORMAT_XVYU16161616:
> > > + return 4;
> > > + default:
> > > + return 1;
> > > + }
> > > +}
> > > +
> > > static int icl_max_plane_width(const struct drm_framebuffer *fb,
> > > int color_plane,
> > > unsigned int rotation)
> > > @@ -3831,15 +3870,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> > > int y = plane_state->uapi.src.y1 >> 16;
> > > int w = drm_rect_width(&plane_state->uapi.src) >> 16;
> > > int h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > > - int max_width;
> > > - int max_height;
> > > - u32 alignment;
> > > - u32 offset;
> > > + int max_width, min_width = 1, max_height;
> > > + u32 alignment, offset;
> > > int aux_plane = intel_main_to_aux_plane(fb, 0);
> > > u32 aux_offset = plane_state->color_plane[aux_plane].offset;
> > >
> > > - if (INTEL_GEN(dev_priv) >= 11)
> > > + if (INTEL_GEN(dev_priv) >= 11) {
> > > max_width = icl_max_plane_width(fb, 0, rotation);
> > > + min_width = icl_min_plane_width(dev_priv, fb);
> > > + }
> > > else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > > max_width = glk_max_plane_width(fb, 0, rotation);
> > > else
> > > @@ -3850,10 +3889,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> > > else
> > > max_height = skl_max_plane_height();
> > >
> > > - if (w > max_width || h > max_height) {
> > > + if (w > max_width || w < min_width || h > max_height) {
> > > drm_dbg_kms(&dev_priv->drm,
> > > - "requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
> > > - w, h, max_width, max_height);
> > > + "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
> > > + w, h, min_width, max_width, max_height);
> > > return -EINVAL;
> > > }
> > >
> > > --
> > > 2.21.3
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+
2020-06-16 16:34 [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+ Matt Atwood
2020-06-16 16:39 ` Ville Syrjälä
@ 2020-06-16 17:34 ` Ville Syrjälä
2020-06-18 15:37 ` Aditya Swarup
2020-07-24 22:08 ` Matt Atwood
2020-06-16 20:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (2 subsequent siblings)
4 siblings, 2 replies; 12+ messages in thread
From: Ville Syrjälä @ 2020-06-16 17:34 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
On Tue, Jun 16, 2020 at 09:34:06AM -0700, Matt Atwood wrote:
> Add minimum width to planes, variable with specific formats, for gen11+.
>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 55 +++++++++++++++++---
> 1 file changed, 47 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7457813ef273..d4fdad6cb3b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3760,6 +3760,45 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb,
> }
> }
>
> +static int icl_min_plane_width(struct drm_i915_private *dev_priv,
> + const struct drm_framebuffer *fb)
> +{
> + /* Wa_14011264657, Wa_14011050563 */
> + switch (fb->format->format) {
> + case DRM_FORMAT_C8:
> + return 18;
> + case DRM_FORMAT_RGB565:
> + return 10;
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_ABGR8888:
> + case DRM_FORMAT_XRGB2101010:
> + case DRM_FORMAT_XBGR2101010:
> + case DRM_FORMAT_ARGB2101010:
> + case DRM_FORMAT_ABGR2101010:
> + case DRM_FORMAT_XVYU2101010:
> + case DRM_FORMAT_Y212:
> + case DRM_FORMAT_Y216:
> + return 6;
> + case DRM_FORMAT_NV12:
> + return 20;
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> + return 12;
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> + case DRM_FORMAT_XVYU12_16161616:
> + case DRM_FORMAT_XVYU16161616:
> + return 4;
> + default:
> + return 1;
> + }
if (semiplanar) {
switch (cpp[0]) {
case 1:
return 20;
case 2:
return 12;
}
} else {
switch (cpp[0]) {
case 1:
return 18;
case 2:
return 10;
case 4:
return 6;
case 8:
return 4;
}
}
Actually if we fully reverse engineer this we are left with just:
if (semiplanar)
return 16/cpp[0] + 4;
else
return 16/cpp[0] + 2;
I'd much prefer calculating this since then it's fully divorced from
defining new pixel formats. Can we get a confirmation from the hw
folks if that is in fact the formula (or if there's a different formula
how they came up with these magic numbers)?
> +}
> +
> static int icl_max_plane_width(const struct drm_framebuffer *fb,
> int color_plane,
> unsigned int rotation)
> @@ -3831,15 +3870,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> int y = plane_state->uapi.src.y1 >> 16;
> int w = drm_rect_width(&plane_state->uapi.src) >> 16;
> int h = drm_rect_height(&plane_state->uapi.src) >> 16;
> - int max_width;
> - int max_height;
> - u32 alignment;
> - u32 offset;
> + int max_width, min_width = 1, max_height;
> + u32 alignment, offset;
> int aux_plane = intel_main_to_aux_plane(fb, 0);
> u32 aux_offset = plane_state->color_plane[aux_plane].offset;
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (INTEL_GEN(dev_priv) >= 11) {
> max_width = icl_max_plane_width(fb, 0, rotation);
> + min_width = icl_min_plane_width(dev_priv, fb);
> + }
> else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
Missing curly braces on all the branches. Feels like dejavu...
I'd also do the min_width=1 assignment in each branch to make it
clear what's what.
> max_width = glk_max_plane_width(fb, 0, rotation);
> else
> @@ -3850,10 +3889,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> else
> max_height = skl_max_plane_height();
>
> - if (w > max_width || h > max_height) {
> + if (w > max_width || w < min_width || h > max_height) {
> drm_dbg_kms(&dev_priv->drm,
> - "requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
> - w, h, max_width, max_height);
> + "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
> + w, h, min_width, max_width, max_height);
> return -EINVAL;
> }
>
> --
> 2.21.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+
2020-06-16 17:34 ` Ville Syrjälä
@ 2020-06-18 15:37 ` Aditya Swarup
2020-07-24 22:08 ` Matt Atwood
1 sibling, 0 replies; 12+ messages in thread
From: Aditya Swarup @ 2020-06-18 15:37 UTC (permalink / raw)
To: Ville Syrjälä, Matt Atwood; +Cc: intel-gfx
On 6/16/20 10:34 AM, Ville Syrjälä wrote:
> On Tue, Jun 16, 2020 at 09:34:06AM -0700, Matt Atwood wrote:
>> Add minimum width to planes, variable with specific formats, for gen11+.
>>
>> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 55 +++++++++++++++++---
>> 1 file changed, 47 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 7457813ef273..d4fdad6cb3b1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -3760,6 +3760,45 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb,
>> }
>> }
>>
>> +static int icl_min_plane_width(struct drm_i915_private *dev_priv,
>> + const struct drm_framebuffer *fb)
>> +{
>> + /* Wa_14011264657, Wa_14011050563 */
>> + switch (fb->format->format) {
>> + case DRM_FORMAT_C8:
>> + return 18;
>> + case DRM_FORMAT_RGB565:
>> + return 10;
>> + case DRM_FORMAT_XRGB8888:
>> + case DRM_FORMAT_XBGR8888:
>> + case DRM_FORMAT_ARGB8888:
>> + case DRM_FORMAT_ABGR8888:
>> + case DRM_FORMAT_XRGB2101010:
>> + case DRM_FORMAT_XBGR2101010:
>> + case DRM_FORMAT_ARGB2101010:
>> + case DRM_FORMAT_ABGR2101010:
>> + case DRM_FORMAT_XVYU2101010:
>> + case DRM_FORMAT_Y212:
>> + case DRM_FORMAT_Y216:
>> + return 6;
>> + case DRM_FORMAT_NV12:
>> + return 20;
>> + case DRM_FORMAT_P010:
>> + case DRM_FORMAT_P012:
>> + case DRM_FORMAT_P016:
>> + return 12;
>> + case DRM_FORMAT_XRGB16161616F:
>> + case DRM_FORMAT_XBGR16161616F:
>> + case DRM_FORMAT_ARGB16161616F:
>> + case DRM_FORMAT_ABGR16161616F:
>> + case DRM_FORMAT_XVYU12_16161616:
>> + case DRM_FORMAT_XVYU16161616:
>> + return 4;
>> + default:
>> + return 1;
>> + }
>
> if (semiplanar) {
> switch (cpp[0]) {
> case 1:
> return 20;
> case 2:
> return 12;
> }
> } else {
> switch (cpp[0]) {
> case 1:
> return 18;
> case 2:
> return 10;
> case 4:
> return 6;
> case 8:
> return 4;
> }
> }
>
> Actually if we fully reverse engineer this we are left with just:
> if (semiplanar)
> return 16/cpp[0] + 4;
> else
> return 16/cpp[0] + 2;
>
> I'd much prefer calculating this since then it's fully divorced from
> defining new pixel formats. Can we get a confirmation from the hw
> folks if that is in fact the formula (or if there's a different formula
> how they came up with these magic numbers)?
>
>> +}
>> +
>> static int icl_max_plane_width(const struct drm_framebuffer *fb,
>> int color_plane,
>> unsigned int rotation)
>> @@ -3831,15 +3870,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
>> int y = plane_state->uapi.src.y1 >> 16;
>> int w = drm_rect_width(&plane_state->uapi.src) >> 16;
>> int h = drm_rect_height(&plane_state->uapi.src) >> 16;
>> - int max_width;
>> - int max_height;
>> - u32 alignment;
>> - u32 offset;
>> + int max_width, min_width = 1, max_height;
>> + u32 alignment, offset;
>> int aux_plane = intel_main_to_aux_plane(fb, 0);
>> u32 aux_offset = plane_state->color_plane[aux_plane].offset;
>>
>> - if (INTEL_GEN(dev_priv) >= 11)
>> + if (INTEL_GEN(dev_priv) >= 11) {
>> max_width = icl_max_plane_width(fb, 0, rotation);
>> + min_width = icl_min_plane_width(dev_priv, fb);
To add to Ville's comments, there is no need for dev_priv and while we are at it, I don't understand
the significance of passing parameters rotation if we are not going to use it?
Aditya
>> + }
>> else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>
> Missing curly braces on all the branches. Feels like dejavu...
>
> I'd also do the min_width=1 assignment in each branch to make it
> clear what's what.
>
>> max_width = glk_max_plane_width(fb, 0, rotation);
>> else
>> @@ -3850,10 +3889,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
>> else
>> max_height = skl_max_plane_height();
>>
>> - if (w > max_width || h > max_height) {
>> + if (w > max_width || w < min_width || h > max_height) {
>> drm_dbg_kms(&dev_priv->drm,
>> - "requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
>> - w, h, max_width, max_height);
>> + "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
>> + w, h, min_width, max_width, max_height);
>> return -EINVAL;
>> }
>>
>> --
>> 2.21.3
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+
2020-06-16 17:34 ` Ville Syrjälä
2020-06-18 15:37 ` Aditya Swarup
@ 2020-07-24 22:08 ` Matt Atwood
1 sibling, 0 replies; 12+ messages in thread
From: Matt Atwood @ 2020-07-24 22:08 UTC (permalink / raw)
To: Ville Syrjälä, intel-gfx
On Tue, Jun 16, 2020 at 08:34:07PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 16, 2020 at 09:34:06AM -0700, Matt Atwood wrote:
> > Add minimum width to planes, variable with specific formats, for gen11+.
> >
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 55 +++++++++++++++++---
> > 1 file changed, 47 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 7457813ef273..d4fdad6cb3b1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -3760,6 +3760,45 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb,
> > }
> > }
> >
> > +static int icl_min_plane_width(struct drm_i915_private *dev_priv,
> > + const struct drm_framebuffer *fb)
> > +{
> > + /* Wa_14011264657, Wa_14011050563 */
> > + switch (fb->format->format) {
> > + case DRM_FORMAT_C8:
> > + return 18;
> > + case DRM_FORMAT_RGB565:
> > + return 10;
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_ARGB8888:
> > + case DRM_FORMAT_ABGR8888:
> > + case DRM_FORMAT_XRGB2101010:
> > + case DRM_FORMAT_XBGR2101010:
> > + case DRM_FORMAT_ARGB2101010:
> > + case DRM_FORMAT_ABGR2101010:
> > + case DRM_FORMAT_XVYU2101010:
> > + case DRM_FORMAT_Y212:
> > + case DRM_FORMAT_Y216:
> > + return 6;
> > + case DRM_FORMAT_NV12:
> > + return 20;
> > + case DRM_FORMAT_P010:
> > + case DRM_FORMAT_P012:
> > + case DRM_FORMAT_P016:
> > + return 12;
> > + case DRM_FORMAT_XRGB16161616F:
> > + case DRM_FORMAT_XBGR16161616F:
> > + case DRM_FORMAT_ARGB16161616F:
> > + case DRM_FORMAT_ABGR16161616F:
> > + case DRM_FORMAT_XVYU12_16161616:
> > + case DRM_FORMAT_XVYU16161616:
> > + return 4;
> > + default:
> > + return 1;
> > + }
>
> if (semiplanar) {
> switch (cpp[0]) {
> case 1:
> return 20;
> case 2:
> return 12;
> }
> } else {
> switch (cpp[0]) {
> case 1:
> return 18;
> case 2:
> return 10;
> case 4:
> return 6;
> case 8:
> return 4;
> }
> }
>
> Actually if we fully reverse engineer this we are left with just:
> if (semiplanar)
> return 16/cpp[0] + 4;
> else
> return 16/cpp[0] + 2;
>
> I'd much prefer calculating this since then it's fully divorced from
> defining new pixel formats. Can we get a confirmation from the hw
> folks if that is in fact the formula (or if there's a different formula
> how they came up with these magic numbers)?
Verified with hardware folks the above doesnt always work for some of
the cases that we need to support.
>
> > +}
> > +
> > static int icl_max_plane_width(const struct drm_framebuffer *fb,
> > int color_plane,
> > unsigned int rotation)
> > @@ -3831,15 +3870,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> > int y = plane_state->uapi.src.y1 >> 16;
> > int w = drm_rect_width(&plane_state->uapi.src) >> 16;
> > int h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > - int max_width;
> > - int max_height;
> > - u32 alignment;
> > - u32 offset;
> > + int max_width, min_width = 1, max_height;
> > + u32 alignment, offset;
> > int aux_plane = intel_main_to_aux_plane(fb, 0);
> > u32 aux_offset = plane_state->color_plane[aux_plane].offset;
> >
> > - if (INTEL_GEN(dev_priv) >= 11)
> > + if (INTEL_GEN(dev_priv) >= 11) {
> > max_width = icl_max_plane_width(fb, 0, rotation);
> > + min_width = icl_min_plane_width(dev_priv, fb);
> > + }
> > else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>
> Missing curly braces on all the branches. Feels like dejavu...
>
> I'd also do the min_width=1 assignment in each branch to make it
> clear what's what.
>
> > max_width = glk_max_plane_width(fb, 0, rotation);
> > else
> > @@ -3850,10 +3889,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> > else
> > max_height = skl_max_plane_height();
> >
> > - if (w > max_width || h > max_height) {
> > + if (w > max_width || w < min_width || h > max_height) {
> > drm_dbg_kms(&dev_priv->drm,
> > - "requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
> > - w, h, max_width, max_height);
> > + "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
> > + w, h, min_width, max_width, max_height);
> > return -EINVAL;
> > }
> >
> > --
> > 2.21.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Apply Wa_14011264657:gen11+
2020-06-16 16:34 [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+ Matt Atwood
2020-06-16 16:39 ` Ville Syrjälä
2020-06-16 17:34 ` Ville Syrjälä
@ 2020-06-16 20:20 ` Patchwork
2020-06-16 20:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-16 23:48 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2020-06-16 20:20 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Apply Wa_14011264657:gen11+
URL : https://patchwork.freedesktop.org/series/78430/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
71e1726c303a drm/i915: Apply Wa_14011264657:gen11+
-:19: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#19: FILE: drivers/gpu/drm/i915/display/intel_display.c:3764:
+static int icl_min_plane_width(struct drm_i915_private *dev_priv,
+ const struct drm_framebuffer *fb)
-:74: CHECK:BRACES: braces {} should be used on all arms of this statement
#74: FILE: drivers/gpu/drm/i915/display/intel_display.c:3878:
+ if (INTEL_GEN(dev_priv) >= 11) {
[...]
else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
[...]
total: 0 errors, 0 warnings, 2 checks, 78 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Apply Wa_14011264657:gen11+
2020-06-16 16:34 [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+ Matt Atwood
` (2 preceding siblings ...)
2020-06-16 20:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2020-06-16 20:43 ` Patchwork
2020-06-16 23:48 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2020-06-16 20:43 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Apply Wa_14011264657:gen11+
URL : https://patchwork.freedesktop.org/series/78430/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8635 -> Patchwork_17966
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/index.html
Known issues
------------
Here are the changes found in Patchwork_17966 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-icl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-guc/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-icl-guc/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@active:
- fi-skl-6600u: [PASS][5] -> [DMESG-FAIL][6] ([i915#666])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-skl-6600u/igt@i915_selftest@live@active.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-skl-6600u/igt@i915_selftest@live@active.html
* igt@i915_selftest@live@coherency:
- fi-gdg-551: [PASS][7] -> [DMESG-FAIL][8] ([i915#1748])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-gdg-551/igt@i915_selftest@live@coherency.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-gdg-551/igt@i915_selftest@live@coherency.html
* igt@i915_selftest@live@gem_contexts:
- fi-tgl-u2: [PASS][9] -> [INCOMPLETE][10] ([i915#1932])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-tgl-u2/igt@i915_selftest@live@gem_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-tgl-u2/igt@i915_selftest@live@gem_contexts.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-tgl-u2: [PASS][13] -> [DMESG-WARN][14] ([i915#402])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-tgl-u2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-tgl-u2/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-kbl-x1275/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-guc: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-icl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569
[i915#1748]: https://gitlab.freedesktop.org/drm/intel/issues/1748
[i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192
[i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193
[i915#1932]: https://gitlab.freedesktop.org/drm/intel/issues/1932
[i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (47 -> 42)
------------------------------
Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8635 -> Patchwork_17966
CI-20190529: 20190529
CI_DRM_8635: f9acdb898773f94ac1bcb9a8826596f88412a53b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17966: 71e1726c303a2e7fd80ac1e3e8a4578ffee856c8 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
71e1726c303a drm/i915: Apply Wa_14011264657:gen11+
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Apply Wa_14011264657:gen11+
2020-06-16 16:34 [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+ Matt Atwood
` (3 preceding siblings ...)
2020-06-16 20:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-06-16 23:48 ` Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2020-06-16 23:48 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Apply Wa_14011264657:gen11+
URL : https://patchwork.freedesktop.org/series/78430/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8635_full -> Patchwork_17966_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17966_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17966_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17966_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_balancer@bonded-early:
- shard-kbl: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl6/igt@gem_exec_balancer@bonded-early.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-kbl7/igt@gem_exec_balancer@bonded-early.html
* igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
- shard-tglb: [PASS][3] -> [FAIL][4] +6 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb7/igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-tglb1/igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format.html
* igt@kms_plane_scaling@pipe-d-scaler-with-pixel-format:
- shard-tglb: NOTRUN -> [FAIL][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-tglb2/igt@kms_plane_scaling@pipe-d-scaler-with-pixel-format.html
Known issues
------------
Here are the changes found in Patchwork_17966_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-mixed-process@rcs0:
- shard-skl: [PASS][6] -> [FAIL][7] ([i915#1528])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl7/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-skl3/igt@gem_ctx_persistence@engines-mixed-process@rcs0.html
* igt@gem_exec_flush@basic-wb-rw-before-default:
- shard-apl: [PASS][8] -> [DMESG-WARN][9] ([i915#95]) +17 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl8/igt@gem_exec_flush@basic-wb-rw-before-default.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl4/igt@gem_exec_flush@basic-wb-rw-before-default.html
* igt@gem_exec_whisper@basic-contexts-priority-all:
- shard-glk: [PASS][10] -> [DMESG-WARN][11] ([i915#118] / [i915#95])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk4/igt@gem_exec_whisper@basic-contexts-priority-all.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-glk4/igt@gem_exec_whisper@basic-contexts-priority-all.html
* igt@gem_shrink@reclaim:
- shard-hsw: [PASS][12] -> [SKIP][13] ([fdo#109271])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-hsw5/igt@gem_shrink@reclaim.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-hsw1/igt@gem_shrink@reclaim.html
* igt@kms_big_fb@linear-64bpp-rotate-180:
- shard-glk: [PASS][14] -> [DMESG-FAIL][15] ([i915#118] / [i915#95])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk1/igt@kms_big_fb@linear-64bpp-rotate-180.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-glk8/igt@kms_big_fb@linear-64bpp-rotate-180.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-apl: [PASS][16] -> [FAIL][17] ([i915#79])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-kbl: [PASS][18] -> [DMESG-WARN][19] ([i915#180]) +5 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-kbl4/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip_tiling@flip-changes-tiling:
- shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +7 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl8/igt@kms_flip_tiling@flip-changes-tiling.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-skl10/igt@kms_flip_tiling@flip-changes-tiling.html
* igt@kms_flip_tiling@flip-changes-tiling-y:
- shard-apl: [PASS][22] -> [DMESG-FAIL][23] ([i915#95])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl2/igt@kms_flip_tiling@flip-changes-tiling-y.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl3/igt@kms_flip_tiling@flip-changes-tiling-y.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-kbl: [PASS][24] -> [DMESG-WARN][25] ([i915#93] / [i915#95]) +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-tglb: [PASS][26] -> [DMESG-WARN][27] ([i915#1982])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][28] -> [FAIL][29] ([fdo#108145] / [i915#265])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
- shard-iclb: [PASS][30] -> [FAIL][31] ([fdo#109052]) +5 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb3/igt@kms_plane_scaling@pipe-b-scaler-with-rotation.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-iclb4/igt@kms_plane_scaling@pipe-b-scaler-with-rotation.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][32] -> [SKIP][33] ([fdo#109441]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
* igt@perf_pmu@semaphore-busy@rcs0:
- shard-kbl: [PASS][34] -> [FAIL][35] ([i915#1820])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl6/igt@perf_pmu@semaphore-busy@rcs0.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-kbl7/igt@perf_pmu@semaphore-busy@rcs0.html
#### Possible fixes ####
* igt@gem_ctx_freq@sysfs:
- shard-apl: [DMESG-WARN][36] ([i915#95]) -> [PASS][37] +19 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl7/igt@gem_ctx_freq@sysfs.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl8/igt@gem_ctx_freq@sysfs.html
* igt@gem_exec_schedule@smoketest-all:
- shard-glk: [DMESG-WARN][38] ([i915#118] / [i915#95]) -> [PASS][39] +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk5/igt@gem_exec_schedule@smoketest-all.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-glk9/igt@gem_exec_schedule@smoketest-all.html
* igt@gem_exec_schedule@smoketest@bcs0:
- shard-tglb: [INCOMPLETE][40] ([i915#1829]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb1/igt@gem_exec_schedule@smoketest@bcs0.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-tglb2/igt@gem_exec_schedule@smoketest@bcs0.html
* igt@i915_module_load@reload:
- shard-skl: [DMESG-WARN][42] ([i915#1982]) -> [PASS][43] +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl9/igt@i915_module_load@reload.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-skl9/igt@i915_module_load@reload.html
- shard-tglb: [DMESG-WARN][44] ([i915#402]) -> [PASS][45] +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb8/igt@i915_module_load@reload.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-tglb7/igt@i915_module_load@reload.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: [FAIL][46] ([IGT#5]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1:
- shard-glk: [FAIL][48] ([i915#79]) -> [PASS][49] +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][50] ([i915#180]) -> [PASS][51] +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@modeset-vs-vblank-race-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][52] ([i915#165] / [i915#78]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt@kms_flip@modeset-vs-vblank-race-interruptible@a-dp1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-kbl3/igt@kms_flip@modeset-vs-vblank-race-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-apl: [DMESG-WARN][54] ([i915#1982]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
- shard-tglb: [DMESG-WARN][56] ([i915#1982]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][58] ([fdo#109441]) -> [PASS][59] +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
* igt@perf@blocking-parameterized:
- shard-iclb: [FAIL][60] ([i915#1542]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb8/igt@perf@blocking-parameterized.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-iclb1/igt@perf@blocking-parameterized.html
#### Warnings ####
* igt@gem_exec_reloc@basic-concurrent16:
- shard-apl: [INCOMPLETE][62] ([i915#1635] / [i915#1958]) -> [TIMEOUT][63] ([i915#1635] / [i915#1958])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl8/igt@gem_exec_reloc@basic-concurrent16.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl1/igt@gem_exec_reloc@basic-concurrent16.html
* igt@kms_color@pipe-c-ctm-0-25:
- shard-tglb: [DMESG-FAIL][64] ([i915#1149] / [i915#1982]) -> [FAIL][65] ([i915#1149] / [i915#315])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb6/igt@kms_color@pipe-c-ctm-0-25.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-tglb3/igt@kms_color@pipe-c-ctm-0-25.html
* igt@kms_fbcon_fbt@fbc:
- shard-apl: [DMESG-FAIL][66] ([i915#95]) -> [FAIL][67] ([i915#1525])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl4/igt@kms_fbcon_fbt@fbc.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl2/igt@kms_fbcon_fbt@fbc.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [FAIL][68] ([i915#1525]) -> [DMESG-FAIL][69] ([i915#95])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-skl: [FAIL][70] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][71] ([fdo#108145] / [i915#1982])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109052]: https://bugs.freedesktop.org/show_bug.cgi?id=109052
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525
[i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820
[i915#1829]: https://gitlab.freedesktop.org/drm/intel/issues/1829
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8635 -> Patchwork_17966
CI-20190529: 20190529
CI_DRM_8635: f9acdb898773f94ac1bcb9a8826596f88412a53b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17966: 71e1726c303a2e7fd80ac1e3e8a4578ffee856c8 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+
@ 2020-08-12 21:07 Matt Atwood
2020-08-19 22:38 ` Souza, Jose
0 siblings, 1 reply; 12+ messages in thread
From: Matt Atwood @ 2020-08-12 21:07 UTC (permalink / raw)
To: intel-gfx
Add minimum width to planes, variable with specific formats for gen11+
to reflect recent bspec changes.
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 54 +++++++++++++++++---
1 file changed, 46 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2ddabf92adde..b5ebcff8d56e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3762,6 +3762,44 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb,
}
}
+static int icl_min_plane_width(const struct drm_framebuffer *fb)
+{
+ /* Wa_14011264657, Wa_14011050563: gen11+ */
+ switch (fb->format->format) {
+ case DRM_FORMAT_C8:
+ return 18;
+ case DRM_FORMAT_RGB565:
+ return 10;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_XVYU2101010:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
+ return 6;
+ case DRM_FORMAT_NV12:
+ return 20;
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
+ return 12;
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ case DRM_FORMAT_XVYU12_16161616:
+ case DRM_FORMAT_XVYU16161616:
+ return 4;
+ default:
+ return 1;
+ }
+}
+
static int icl_max_plane_width(const struct drm_framebuffer *fb,
int color_plane,
unsigned int rotation)
@@ -3844,15 +3882,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
int y = plane_state->uapi.src.y1 >> 16;
int w = drm_rect_width(&plane_state->uapi.src) >> 16;
int h = drm_rect_height(&plane_state->uapi.src) >> 16;
- int max_width;
- int max_height;
- u32 alignment;
- u32 offset;
+ int max_width, min_width = 1, max_height;
+ u32 alignment, offset;
int aux_plane = intel_main_to_aux_plane(fb, 0);
u32 aux_offset = plane_state->color_plane[aux_plane].offset;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 11) {
max_width = icl_max_plane_width(fb, 0, rotation);
+ min_width = icl_min_plane_width(fb);
+ }
else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
max_width = glk_max_plane_width(fb, 0, rotation);
else
@@ -3863,10 +3901,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
else
max_height = skl_max_plane_height();
- if (w > max_width || h > max_height) {
+ if (w > max_width || w < min_width || h > max_height) {
drm_dbg_kms(&dev_priv->drm,
- "requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
- w, h, max_width, max_height);
+ "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
+ w, h, min_width, max_width, max_height);
return -EINVAL;
}
--
2.21.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+
2020-08-12 21:07 [Intel-gfx] [PATCH] " Matt Atwood
@ 2020-08-19 22:38 ` Souza, Jose
0 siblings, 0 replies; 12+ messages in thread
From: Souza, Jose @ 2020-08-19 22:38 UTC (permalink / raw)
To: Atwood, Matthew S, intel-gfx@lists.freedesktop.org
On Wed, 2020-08-12 at 14:07 -0700, Matt Atwood wrote:
> Add minimum width to planes, variable with specific formats for gen11+
> to reflect recent bspec changes.
>
> Signed-off-by: Matt Atwood <
> matthew.s.atwood@intel.com
> >
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 54 +++++++++++++++++---
> 1 file changed, 46 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2ddabf92adde..b5ebcff8d56e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3762,6 +3762,44 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb,
> }
> }
>
> +static int icl_min_plane_width(const struct drm_framebuffer *fb)
> +{
> + /* Wa_14011264657, Wa_14011050563: gen11+ */
> + switch (fb->format->format) {
> + case DRM_FORMAT_C8:
> + return 18;
> + case DRM_FORMAT_RGB565:
> + return 10;
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_ABGR8888:
> + case DRM_FORMAT_XRGB2101010:
> + case DRM_FORMAT_XBGR2101010:
> + case DRM_FORMAT_ARGB2101010:
> + case DRM_FORMAT_ABGR2101010:
> + case DRM_FORMAT_XVYU2101010:
> + case DRM_FORMAT_Y212:
> + case DRM_FORMAT_Y216:
> + return 6;
> + case DRM_FORMAT_NV12:
> + return 20;
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> + return 12;
> + case DRM_FORMAT_XRGB16161616F:
> + case DRM_FORMAT_XBGR16161616F:
> + case DRM_FORMAT_ARGB16161616F:
> + case DRM_FORMAT_ABGR16161616F:
> + case DRM_FORMAT_XVYU12_16161616:
> + case DRM_FORMAT_XVYU16161616:
> + return 4;
> + default:
> + return 1;
> + }
> +}
> +
> static int icl_max_plane_width(const struct drm_framebuffer *fb,
> int color_plane,
> unsigned int rotation)
> @@ -3844,15 +3882,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> int y = plane_state->uapi.src.y1 >> 16;
> int w = drm_rect_width(&plane_state->uapi.src) >> 16;
> int h = drm_rect_height(&plane_state->uapi.src) >> 16;
> - int max_width;
> - int max_height;
> - u32 alignment;
> - u32 offset;
> + int max_width, min_width = 1, max_height;
> + u32 alignment, offset;
> int aux_plane = intel_main_to_aux_plane(fb, 0);
> u32 aux_offset = plane_state->color_plane[aux_plane].offset;
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (INTEL_GEN(dev_priv) >= 11) {
> max_width = icl_max_plane_width(fb, 0, rotation);
> + min_width = icl_min_plane_width(fb);
> + }
With the style fixed, LGTM.
It is small enough to be fixed while pushing it, will fix and push it for you.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> max_width = glk_max_plane_width(fb, 0, rotation);
> else
> @@ -3863,10 +3901,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> else
> max_height = skl_max_plane_height();
>
> - if (w > max_width || h > max_height) {
> + if (w > max_width || w < min_width || h > max_height) {
> drm_dbg_kms(&dev_priv->drm,
> - "requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
> - w, h, max_width, max_height);
> + "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
> + w, h, min_width, max_width, max_height);
> return -EINVAL;
> }
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-08-19 22:38 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-06-16 16:34 [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+ Matt Atwood
2020-06-16 16:39 ` Ville Syrjälä
2020-06-16 17:01 ` Matt Atwood
2020-06-16 17:06 ` Ville Syrjälä
2020-06-16 17:34 ` Ville Syrjälä
2020-06-18 15:37 ` Aditya Swarup
2020-07-24 22:08 ` Matt Atwood
2020-06-16 20:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-06-16 20:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-16 23:48 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2020-08-12 21:07 [Intel-gfx] [PATCH] " Matt Atwood
2020-08-19 22:38 ` Souza, Jose
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox