* [Intel-gfx] [PATCH v3 01/28] drm/i915: Add has_master_unit_irq flag
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 02/28] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
` (34 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Stuart Summers <stuart.summers@intel.com>
Add flag to differentiate platforms with and without the master
IRQ control bit.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6e9072ab30a1..7e830d94ade8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1597,6 +1597,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
(INTEL_INFO(dev_priv)->has_logical_ring_preemption)
+#define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
+
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 8d62b8538585..770d07003ce6 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -122,6 +122,7 @@ enum intel_ppgtt_type {
func(has_logical_ring_contexts); \
func(has_logical_ring_elsq); \
func(has_logical_ring_preemption); \
+ func(has_master_unit_irq); \
func(has_pooled_eu); \
func(has_rc6); \
func(has_rc6p); \
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 02/28] drm/i915/dg1: add initial DG-1 definitions
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 01/28] drm/i915: Add has_master_unit_irq flag Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
` (33 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Bspec: 33617, 33617
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Vanshidhar Konda <vanshidhar.r.konda@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++++++
drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
4 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7e830d94ade8..2f957aaa20b3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1430,6 +1430,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
+#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
@@ -1558,6 +1559,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_RKL_REVID(p, since, until) \
(IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
+#define DG1_REVID_A0 0x0
+#define DG1_REVID_B0 0x1
+
+#define IS_DG1_REVID(p, since, until) \
+ (IS_DG1(p) && IS_REVID(p, since, until))
+
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e5fdf17cd9cd..58cceeaa0ffa 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -896,8 +896,20 @@ static const struct intel_device_info rkl_info = {
#define GEN12_DGFX_FEATURES \
GEN12_FEATURES, \
+ .memory_regions = REGION_SMEM | REGION_LMEM, \
+ .has_master_unit_irq = 1, \
.is_dgfx = 1
+static const struct intel_device_info intel_dg1_info = {
+ GEN12_DGFX_FEATURES,
+ PLATFORM(INTEL_DG1),
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ .require_force_probe = 1,
+ .engine_mask =
+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
+ BIT(VCS0) | BIT(VCS2),
+};
+
#undef GEN
#undef PLATFORM
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 544ac61fbc36..2e40a6649d14 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -63,6 +63,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(ELKHARTLAKE),
PLATFORM_NAME(TIGERLAKE),
PLATFORM_NAME(ROCKETLAKE),
+ PLATFORM_NAME(DG1),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 770d07003ce6..bdd21cde917c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -82,6 +82,7 @@ enum intel_platform {
/* gen12 */
INTEL_TIGERLAKE,
INTEL_ROCKETLAKE,
+ INTEL_DG1,
INTEL_MAX_PLATFORMS
};
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 01/28] drm/i915: Add has_master_unit_irq flag Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 02/28] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-02 6:00 ` kernel test robot
` (2 more replies)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 04/28] drm/i915/dg1: add support for the master unit interrupt Lucas De Marchi
` (32 subsequent siblings)
35 siblings, 3 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Add the PCI ID for DG1, but keep it out of the table we use to register
the driver. At this point we can't consider the driver ready to bind to
the device since we basically miss support for everything. When more
support is merged we can enable it to work partially for example as a
display-only driver.
v2: remove DG1 from the pci table and reword commit message (Lucas)
Bspec: 44463
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com> # v1
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
include/drm/i915_pciids.h | 4 ++++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 58cceeaa0ffa..8cae64adbb23 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -900,7 +900,7 @@ static const struct intel_device_info rkl_info = {
.has_master_unit_irq = 1, \
.is_dgfx = 1
-static const struct intel_device_info intel_dg1_info = {
+static const struct intel_device_info dg1_info = {
GEN12_DGFX_FEATURES,
PLATFORM(INTEL_DG1),
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index bc989de2aac2..f44fe822880d 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -614,4 +614,8 @@
INTEL_VGA_DEVICE(0x4C90, info), \
INTEL_VGA_DEVICE(0x4C9A, info)
+/* DG1 */
+#define INTEL_DG1_IDS(info) \
+ INTEL_VGA_DEVICE(0x4905, info)
+
#endif /* _I915_PCIIDS_H */
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
@ 2020-07-02 6:00 ` kernel test robot
2020-07-09 20:01 ` Lucas De Marchi
2020-07-02 12:37 ` kernel test robot
2020-07-08 17:08 ` Daniel Vetter
2 siblings, 1 reply; 46+ messages in thread
From: kernel test robot @ 2020-07-02 6:00 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx; +Cc: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 1770 bytes --]
Hi Lucas,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip next-20200701]
[cannot apply to v5.8-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Lucas-De-Marchi/Introduce-DG1/20200702-075819
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-m021-20200701 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-14) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/i915_pci.c:903:39: error: 'dg1_info' defined but not used [-Werror=unused-const-variable=]
903 | static const struct intel_device_info dg1_info = {
| ^~~~~~~~
cc1: all warnings being treated as errors
vim +/dg1_info +903 drivers/gpu/drm/i915/i915_pci.c
896
897 #define GEN12_DGFX_FEATURES \
898 GEN12_FEATURES, \
899 .memory_regions = REGION_SMEM | REGION_LMEM, \
900 .has_master_unit_irq = 1, \
901 .is_dgfx = 1
902
> 903 static const struct intel_device_info dg1_info = {
904 GEN12_DGFX_FEATURES,
905 PLATFORM(INTEL_DG1),
906 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
907 .require_force_probe = 1,
908 .engine_mask =
909 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
910 BIT(VCS0) | BIT(VCS2),
911 };
912
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 41842 bytes --]
[-- Attachment #3: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs
2020-07-02 6:00 ` kernel test robot
@ 2020-07-09 20:01 ` Lucas De Marchi
2020-07-09 20:56 ` Lucas De Marchi
0 siblings, 1 reply; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-09 20:01 UTC (permalink / raw)
To: kernel test robot
Cc: kbuild-all, Intel Graphics, Lucas De Marchi, Daniel Vetter
On Wed, Jul 1, 2020 at 11:01 PM kernel test robot <lkp@intel.com> wrote:
>
> Hi Lucas,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on drm-intel/for-linux-next]
> [also build test ERROR on drm-tip/drm-tip next-20200701]
> [cannot apply to v5.8-rc3]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url: https://github.com/0day-ci/linux/commits/Lucas-De-Marchi/Introduce-DG1/20200702-075819
> base: git://anongit.freedesktop.org/drm-intel for-linux-next
> config: i386-randconfig-m021-20200701 (attached as .config)
> compiler: gcc-9 (Debian 9.3.0-14) 9.3.0
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All errors (new ones prefixed by >>):
>
> >> drivers/gpu/drm/i915/i915_pci.c:903:39: error: 'dg1_info' defined but not used [-Werror=unused-const-variable=]
> 903 | static const struct intel_device_info dg1_info = {
> | ^~~~~~~~
This is intentionally left unused. Wonder what the fix would be...
__attribute__(__unused__) or force the warning
to be ignored here
with or without this change I don't get a warning in gcc 10 (using
the same config attached).
Lucas De Marchi
> cc1: all warnings being treated as errors
>
> vim +/dg1_info +903 drivers/gpu/drm/i915/i915_pci.c
>
> 896
> 897 #define GEN12_DGFX_FEATURES \
> 898 GEN12_FEATURES, \
> 899 .memory_regions = REGION_SMEM | REGION_LMEM, \
> 900 .has_master_unit_irq = 1, \
> 901 .is_dgfx = 1
> 902
> > 903 static const struct intel_device_info dg1_info = {
> 904 GEN12_DGFX_FEATURES,
> 905 PLATFORM(INTEL_DG1),
> 906 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> 907 .require_force_probe = 1,
> 908 .engine_mask =
> 909 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
> 910 BIT(VCS0) | BIT(VCS2),
> 911 };
> 912
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs
2020-07-09 20:01 ` Lucas De Marchi
@ 2020-07-09 20:56 ` Lucas De Marchi
0 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-09 20:56 UTC (permalink / raw)
To: kernel test robot
Cc: kbuild-all, Intel Graphics, Lucas De Marchi, Daniel Vetter
On Thu, Jul 9, 2020 at 1:01 PM Lucas De Marchi
<lucas.de.marchi@gmail.com> wrote:
>
> On Wed, Jul 1, 2020 at 11:01 PM kernel test robot <lkp@intel.com> wrote:
> >
> > Hi Lucas,
> >
> > Thank you for the patch! Yet something to improve:
> >
> > [auto build test ERROR on drm-intel/for-linux-next]
> > [also build test ERROR on drm-tip/drm-tip next-20200701]
> > [cannot apply to v5.8-rc3]
> > [If your patch is applied to the wrong git tree, kindly drop us a note.
> > And when submitting patch, we suggest to use as documented in
> > https://git-scm.com/docs/git-format-patch]
> >
> > url: https://github.com/0day-ci/linux/commits/Lucas-De-Marchi/Introduce-DG1/20200702-075819
> > base: git://anongit.freedesktop.org/drm-intel for-linux-next
> > config: i386-randconfig-m021-20200701 (attached as .config)
> > compiler: gcc-9 (Debian 9.3.0-14) 9.3.0
> >
> > If you fix the issue, kindly add following tag as appropriate
> > Reported-by: kernel test robot <lkp@intel.com>
> >
> > All errors (new ones prefixed by >>):
> >
> > >> drivers/gpu/drm/i915/i915_pci.c:903:39: error: 'dg1_info' defined but not used [-Werror=unused-const-variable=]
> > 903 | static const struct intel_device_info dg1_info = {
> > | ^~~~~~~~
>
> This is intentionally left unused. Wonder what the fix would be...
> __attribute__(__unused__) or force the warning
> to be ignored here
>
> with or without this change I don't get a warning in gcc 10 (using
> the same config attached).
Adding W=1 to the command line and this is sufficient to shut up the warning.
Lucas De Marchi
>
> Lucas De Marchi
>
> > cc1: all warnings being treated as errors
> >
> > vim +/dg1_info +903 drivers/gpu/drm/i915/i915_pci.c
> >
> > 896
> > 897 #define GEN12_DGFX_FEATURES \
> > 898 GEN12_FEATURES, \
> > 899 .memory_regions = REGION_SMEM | REGION_LMEM, \
> > 900 .has_master_unit_irq = 1, \
> > 901 .is_dgfx = 1
> > 902
> > > 903 static const struct intel_device_info dg1_info = {
> > 904 GEN12_DGFX_FEATURES,
> > 905 PLATFORM(INTEL_DG1),
> > 906 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> > 907 .require_force_probe = 1,
> > 908 .engine_mask =
> > 909 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
> > 910 BIT(VCS0) | BIT(VCS2),
> > 911 };
> > 912
> >
> > ---
> > 0-DAY CI Kernel Test Service, Intel Corporation
> > https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Lucas De Marchi
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
2020-07-02 6:00 ` kernel test robot
@ 2020-07-02 12:37 ` kernel test robot
2020-07-08 17:08 ` Daniel Vetter
2 siblings, 0 replies; 46+ messages in thread
From: kernel test robot @ 2020-07-02 12:37 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx; +Cc: clang-built-linux, kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2222 bytes --]
Hi Lucas,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20200702]
[cannot apply to v5.8-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Lucas-De-Marchi/Introduce-DG1/20200702-075819
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-r025-20200702 (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 003a086ffc0d1affbb8300b36225fb8150a2d40a)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/i915_pci.c:903:39: warning: unused variable 'dg1_info' [-Wunused-const-variable]
static const struct intel_device_info dg1_info = {
^
1 warning generated.
vim +/dg1_info +903 drivers/gpu/drm/i915/i915_pci.c
896
897 #define GEN12_DGFX_FEATURES \
898 GEN12_FEATURES, \
899 .memory_regions = REGION_SMEM | REGION_LMEM, \
900 .has_master_unit_irq = 1, \
901 .is_dgfx = 1
902
> 903 static const struct intel_device_info dg1_info = {
904 GEN12_DGFX_FEATURES,
905 PLATFORM(INTEL_DG1),
906 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
907 .require_force_probe = 1,
908 .engine_mask =
909 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
910 BIT(VCS0) | BIT(VCS2),
911 };
912
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 33412 bytes --]
[-- Attachment #3: Type: text/plain, Size: 160 bytes --]
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^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
2020-07-02 6:00 ` kernel test robot
2020-07-02 12:37 ` kernel test robot
@ 2020-07-08 17:08 ` Daniel Vetter
2 siblings, 0 replies; 46+ messages in thread
From: Daniel Vetter @ 2020-07-08 17:08 UTC (permalink / raw)
To: Lucas De Marchi, Dave Airlie; +Cc: intel-gfx
On Thu, Jul 2, 2020 at 1:55 AM Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>
> From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
>
> Add the PCI ID for DG1, but keep it out of the table we use to register
> the driver. At this point we can't consider the driver ready to bind to
> the device since we basically miss support for everything. When more
> support is merged we can enable it to work partially for example as a
> display-only driver.
>
> v2: remove DG1 from the pci table and reword commit message (Lucas)
>
> Bspec: 44463
>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> # v1
> ---
> drivers/gpu/drm/i915/i915_pci.c | 2 +-
> include/drm/i915_pciids.h | 4 ++++
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 58cceeaa0ffa..8cae64adbb23 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -900,7 +900,7 @@ static const struct intel_device_info rkl_info = {
> .has_master_unit_irq = 1, \
> .is_dgfx = 1
>
> -static const struct intel_device_info intel_dg1_info = {
> +static const struct intel_device_info dg1_info = {
Looks like a misplaced hunk here, but aside from that, on the "let's
just not add the pci id":
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Also adding Dave just as fyi.
-Daniel
> GEN12_DGFX_FEATURES,
> PLATFORM(INTEL_DG1),
> .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index bc989de2aac2..f44fe822880d 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -614,4 +614,8 @@
> INTEL_VGA_DEVICE(0x4C90, info), \
> INTEL_VGA_DEVICE(0x4C9A, info)
>
> +/* DG1 */
> +#define INTEL_DG1_IDS(info) \
> + INTEL_VGA_DEVICE(0x4905, info)
> +
> #endif /* _I915_PCIIDS_H */
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v3 04/28] drm/i915/dg1: add support for the master unit interrupt
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (2 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 03/28] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 05/28] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Lucas De Marchi
` (31 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
DG1 has master unit interrupt register which is used to indicate the
correct source of interrupt.
v2: fix coding style on register definition
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Daniele Spurio Ceraolo <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +++
drivers/gpu/drm/i915/i915_irq.c | 56 +++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 4 +++
3 files changed, 61 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 9ca94a435b75..b76a61ec2190 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -492,6 +492,10 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
seq_printf(m, "PCU interrupt enable:\t%08x\n",
I915_READ(GEN8_PCU_IER));
} else if (INTEL_GEN(dev_priv) >= 11) {
+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
+ seq_printf(m, "Master Unit Interrupt Control: %08x\n",
+ I915_READ(DG1_MSTR_UNIT_INTR));
+
seq_printf(m, "Master Interrupt Control: %08x\n",
I915_READ(GEN11_GFX_MSTR_IRQ));
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 562b43ed077f..4c9d0a4a2476 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2584,6 +2584,46 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
gen11_master_intr_enable);
}
+static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
+{
+ u32 val;
+
+ /* First disable interrupts */
+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
+
+ /* Get the indication levels and ack the master unit */
+ val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
+ if (unlikely(!val))
+ return 0;
+
+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
+
+ /*
+ * Now with master disabled, get a sample of level indications
+ * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
+ * out as this bit doesn't exist anymore for DG1
+ */
+ val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
+ if (unlikely(!val))
+ return 0;
+
+ raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
+
+ return val;
+}
+
+static inline void dg1_master_intr_enable(void __iomem * const regs)
+{
+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
+}
+
+static irqreturn_t dg1_irq_handler(int irq, void *arg)
+{
+ return __gen11_irq_handler(arg,
+ dg1_master_intr_disable_and_ack,
+ dg1_master_intr_enable);
+}
+
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
@@ -2920,7 +2960,10 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
- gen11_master_intr_disable(dev_priv->uncore.regs);
+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
+ dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
+ else
+ gen11_master_intr_disable(dev_priv->uncore.regs);
gen11_gt_irq_reset(&dev_priv->gt);
gen11_display_irq_reset(dev_priv);
@@ -3517,8 +3560,13 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
- gen11_master_intr_enable(uncore->regs);
- POSTING_READ(GEN11_GFX_MSTR_IRQ);
+ if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
+ dg1_master_intr_enable(uncore->regs);
+ POSTING_READ(DG1_MSTR_UNIT_INTR);
+ } else {
+ gen11_master_intr_enable(uncore->regs);
+ POSTING_READ(GEN11_GFX_MSTR_IRQ);
+ }
}
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -4043,6 +4091,8 @@ static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
else
return i8xx_irq_handler;
} else {
+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
+ return dg1_irq_handler;
if (INTEL_GEN(dev_priv) >= 11)
return gen11_irq_handler;
else if (INTEL_GEN(dev_priv) >= 8)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9d6536afc94b..ed1b8151ce72 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7723,6 +7723,10 @@ enum {
#define GEN11_GT_DW1_IRQ (1 << 1)
#define GEN11_GT_DW0_IRQ (1 << 0)
+#define DG1_MSTR_UNIT_INTR _MMIO(0x190008)
+#define DG1_MSTR_IRQ REG_BIT(31)
+#define DG1_MSTR_UNIT(u) REG_BIT(u)
+
#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 05/28] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (3 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 04/28] drm/i915/dg1: add support for the master unit interrupt Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 06/28] drm/i915/dg1: Add fake PCH Lucas De Marchi
` (30 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Bspec asks us to remove the special programming of the
SHPD_FILTER_CNT register which we have been doing since CNP+.
Bspec: 49305
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4c9d0a4a2476..1fa67700d8f4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3114,7 +3114,8 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
hotplug_irqs = sde_ddi_mask | sde_tc_mask;
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
- I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
+ if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
+ I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 06/28] drm/i915/dg1: Add fake PCH
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (4 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 05/28] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-08 7:28 ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 07/28] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
` (29 subsequent siblings)
35 siblings, 1 reply; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
DG1 has the south engine display on the same PCI device. Ideally we
could use HAS_PCH_SPLIT(), but that macro is misused all across the
code base to rather signify a range of gens. So add a fake one for DG1
to be used where needed.
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_pch.c | 6 ++++++
drivers/gpu/drm/i915/intel_pch.h | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index c668e99eb2e4..6c97192e9ca8 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -188,6 +188,12 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
{
struct pci_dev *pch = NULL;
+ /* DG1 has south engine display on the same PCI device */
+ if (IS_DG1(dev_priv)) {
+ dev_priv->pch_type = PCH_DG1;
+ return;
+ }
+
/*
* The reason to probe ISA bridge instead of Dev31:Fun0 is to
* make graphics device passthrough work easy for VMM, that only
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 3053d1ce398b..06d2cd50af0b 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -26,6 +26,9 @@ enum intel_pch {
PCH_JSP, /* Jasper Lake PCH */
PCH_MCC, /* Mule Creek Canyon PCH */
PCH_TGP, /* Tiger Lake PCH */
+
+ /* Fake PCHs, functionality handled on the same PCI dev */
+ PCH_DG1 = 1024,
};
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
@@ -56,6 +59,7 @@ enum intel_pch {
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
+#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [Intel-gfx] [PATCH v3 06/28] drm/i915/dg1: Add fake PCH
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 06/28] drm/i915/dg1: Add fake PCH Lucas De Marchi
@ 2020-07-08 7:28 ` Srivatsa, Anusha
0 siblings, 0 replies; 46+ messages in thread
From: Srivatsa, Anusha @ 2020-07-08 7:28 UTC (permalink / raw)
To: De Marchi, Lucas, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Lucas De Marchi
> Sent: Thursday, July 2, 2020 5:23 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 06/28] drm/i915/dg1: Add fake PCH
>
> DG1 has the south engine display on the same PCI device. Ideally we could
> use HAS_PCH_SPLIT(), but that macro is misused all across the code base to
> rather signify a range of gens. So add a fake one for DG1 to be used where
> needed.
>
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pch.c | 6 ++++++
> drivers/gpu/drm/i915/intel_pch.h | 4 ++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pch.c
> b/drivers/gpu/drm/i915/intel_pch.c
> index c668e99eb2e4..6c97192e9ca8 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -188,6 +188,12 @@ void intel_detect_pch(struct drm_i915_private
> *dev_priv) {
> struct pci_dev *pch = NULL;
>
> + /* DG1 has south engine display on the same PCI device */
> + if (IS_DG1(dev_priv)) {
> + dev_priv->pch_type = PCH_DG1;
> + return;
> + }
> +
> /*
> * The reason to probe ISA bridge instead of Dev31:Fun0 is to
> * make graphics device passthrough work easy for VMM, that only
> diff --git a/drivers/gpu/drm/i915/intel_pch.h
> b/drivers/gpu/drm/i915/intel_pch.h
> index 3053d1ce398b..06d2cd50af0b 100644
> --- a/drivers/gpu/drm/i915/intel_pch.h
> +++ b/drivers/gpu/drm/i915/intel_pch.h
> @@ -26,6 +26,9 @@ enum intel_pch {
> PCH_JSP, /* Jasper Lake PCH */
> PCH_MCC, /* Mule Creek Canyon PCH */
> PCH_TGP, /* Tiger Lake PCH */
> +
> + /* Fake PCHs, functionality handled on the same PCI dev */
> + PCH_DG1 = 1024,
> };
>
> #define INTEL_PCH_DEVICE_ID_MASK 0xff80
> @@ -56,6 +59,7 @@ enum intel_pch {
>
> #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
> #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
> +#define HAS_PCH_DG1(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
> #define HAS_PCH_JSP(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
> #define HAS_PCH_MCC(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
> #define HAS_PCH_TGP(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v3 07/28] drm/i915/dg1: Initialize RAWCLK properly
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (5 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 06/28] drm/i915/dg1: Add fake PCH Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 08/28] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
` (28 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
DG1 always uses a 38.4 MHz rawclk rather than the 19.2/24 MHz
frequencies on CNP+. Note that register bits associated with this
frequency confusingly use 37 for the divider field rather than 38 as you
might expect.
For simplicity, let's just assume that this 38.4 MHz frequency will hold
true for other future platforms with "fake" PCH south displays and that
the CNP-style behavior will remain for other platforms with a real PCH.
Bspec: 49950
Bspec: 49309
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 45f7f33d1144..3aea30ba9f74 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2673,6 +2673,18 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
}
+static int dg1_rawclk(struct drm_i915_private *dev_priv)
+{
+ /*
+ * DG1 always uses a 38.4 MHz rawclk. The bspec tells us
+ * "Program Numerator=2, Denominator=4, Divider=37 decimal."
+ */
+ I915_WRITE(PCH_RAWCLK_FREQ,
+ CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
+
+ return 38400;
+}
+
static int cnp_rawclk(struct drm_i915_private *dev_priv)
{
u32 rawclk;
@@ -2781,7 +2793,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
{
u32 freq;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ freq = dg1_rawclk(dev_priv);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
freq = cnp_rawclk(dev_priv);
else if (HAS_PCH_SPLIT(dev_priv))
freq = pch_rawclk(dev_priv);
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 08/28] drm/i915/dg1: Define MOCS table for DG1
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (6 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 07/28] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 09/28] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
` (27 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
DG1 has a new MOCS table. We still use the old definition of the table,
but as for any dgfx card it doesn't contain the control_value values
(these values don't matter as we won't program them).
Bspec: 45101
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 39 +++++++++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 632e08a4592b..7217c6e2087c 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -280,6 +280,39 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
GEN11_MOCS_ENTRIES
};
+static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
+ /* Error */
+ MOCS_ENTRY(0, 0, L3_0_DIRECT),
+
+ /* UC */
+ MOCS_ENTRY(1, 0, L3_1_UC),
+
+ /* Reserved */
+ MOCS_ENTRY(2, 0, L3_0_DIRECT),
+ MOCS_ENTRY(3, 0, L3_0_DIRECT),
+ MOCS_ENTRY(4, 0, L3_0_DIRECT),
+
+ /* WB - L3 */
+ MOCS_ENTRY(5, 0, L3_3_WB),
+ /* WB - L3 50% */
+ MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
+ /* WB - L3 25% */
+ MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
+ /* WB - L3 12.5% */
+ MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
+
+ /* HDC:L1 + L3 */
+ MOCS_ENTRY(48, 0, L3_3_WB),
+ /* HDC:L1 */
+ MOCS_ENTRY(49, 0, L3_1_UC),
+
+ /* HW Reserved */
+ MOCS_ENTRY(60, 0, L3_1_UC),
+ MOCS_ENTRY(61, 0, L3_1_UC),
+ MOCS_ENTRY(62, 0, L3_1_UC),
+ MOCS_ENTRY(63, 0, L3_1_UC),
+};
+
enum {
HAS_GLOBAL_MOCS = BIT(0),
HAS_ENGINE_MOCS = BIT(1),
@@ -306,7 +339,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
{
unsigned int flags;
- if (INTEL_GEN(i915) >= 12) {
+ if (IS_DG1(i915)) {
+ table->size = ARRAY_SIZE(dg1_mocs_table);
+ table->table = dg1_mocs_table;
+ table->n_entries = GEN11_NUM_MOCS_ENTRIES;
+ } else if (INTEL_GEN(i915) >= 12) {
table->size = ARRAY_SIZE(tgl_mocs_table);
table->table = tgl_mocs_table;
table->n_entries = GEN11_NUM_MOCS_ENTRIES;
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 09/28] drm/i915/dg1: Add DG1 power wells
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (7 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 08/28] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 10/28] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
` (26 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Uma Shankar <uma.shankar@intel.com>
Most of TGL power wells are re-used for DG1. However, AUDIO Power
Domain is moved from PG3 to PG0. Handle the change and initialize
power wells with the new power well structure.
Some of the Audio Streaming logic still remains in PW3 so still
it needs to be enabled.
DDIA, DDIB, TC1 and TC2 are the active ports on DG1.
Need to keep Transcoder C and D to Pipe Power wells, this is against
the spec but else hitting unclaimed register warnings (kept the logic
same as TGL)
Bspec: 49182
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../drm/i915/display/intel_display_power.c | 201 +++++++++++++++++-
1 file changed, 200 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 8a277dfbc070..3dc14a9ee00e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2970,6 +2970,44 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define DG1_PW_5_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_4_POWER_DOMAINS ( \
+ DG1_PW_5_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_3_POWER_DOMAINS ( \
+ DG1_PW_4_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_2_POWER_DOMAINS ( \
+ DG1_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ DG1_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = i9xx_always_on_power_well_noop,
@@ -4474,6 +4512,165 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
};
+static const struct i915_power_well_desc dg1_power_wells[] = {
+ {
+ .name = "always-on",
+ .always_on = true,
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
+ {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .always_on = true,
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DC off",
+ .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ },
+ {
+ .name = "power well 2",
+ .domains = DG1_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "power well 3",
+ .domains = DG1_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = ICL_DISP_PW_3,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ }
+ },
+ {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ }
+ },
+ {
+ .name = "DDI D TC1 IO",
+ .domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+ },
+ },
+ {
+ .name = "DDI E TC2 IO",
+ .domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+ },
+ },
+ {
+ .name = "AUX A",
+ .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ },
+ {
+ .name = "AUX B",
+ .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
+ },
+ {
+ .name = "AUX D TC1",
+ .domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX E TC2",
+ .domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "power well 4",
+ .domains = DG1_PW_4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ }
+ },
+ {
+ .name = "power well 5",
+ .domains = DG1_PW_5_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ },
+ },
+};
+
static int
sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
int disable_power_well)
@@ -4622,7 +4819,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ err = set_power_wells(power_domains, dg1_power_wells);
+ } else if (IS_ROCKETLAKE(dev_priv)) {
err = set_power_wells(power_domains, rkl_power_wells);
} else if (IS_GEN(dev_priv, 12)) {
err = set_power_wells(power_domains, tgl_power_wells);
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 10/28] drm/i915/dg1: Increase mmio size to 4MB
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (8 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 09/28] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 11/28] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
` (25 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
On dgfx register range has been extended to go up to 4MB.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michael J. Ruhl <michael.j.ruhl@intel.com>
Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 592364aed2da..49d2cfb55bb2 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1699,11 +1699,15 @@ static int uncore_mmio_setup(struct intel_uncore *uncore)
* clobbering the GTT which we want ioremap_wc instead. Fortunately,
* the register BAR remains the same size for all the earlier
* generations up to Ironlake.
+ * For dgfx chips register range is expanded to 4MB.
*/
if (INTEL_GEN(i915) < 5)
mmio_size = 512 * 1024;
+ else if (IS_DGFX(i915))
+ mmio_size = 4 * 1024 * 1024;
else
mmio_size = 2 * 1024 * 1024;
+
uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
if (uncore->regs == NULL) {
drm_err(&i915->drm, "failed to map registers\n");
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 11/28] drm/i915/dg1: Wait for pcode/uncore handshake at startup
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (9 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 10/28] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 12/28] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
` (24 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
DG1 does some additional pcode/uncore handshaking at
boot time; this handshaking must complete before various other pcode
commands are effective and before general work is submitted to the GPU.
We need to poll a new pcode mailbox during startup until it reports that
this handshaking is complete.
The bspec doesn't give guidance on how long we may need to wait for this
handshaking to complete. For now, let's just set a really long timeout;
if we still don't get a completion status by the end of that timeout,
we'll just continue on and hope for the best.
Bspec: 52065
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++++++++++
drivers/gpu/drm/i915/intel_sideband.h | 2 ++
4 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 67102dc26fce..122e0a5913da 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -85,6 +85,7 @@
#include "intel_gvt.h"
#include "intel_memory_region.h"
#include "intel_pm.h"
+#include "intel_sideband.h"
#include "vlv_suspend.h"
static struct drm_driver driver;
@@ -743,6 +744,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
*/
intel_dram_detect(dev_priv);
+ intel_pcode_init(dev_priv);
+
intel_bw_init_hw(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ed1b8151ce72..bd64272f9844 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9216,6 +9216,9 @@ enum {
#define GEN9_SAGV_DISABLE 0x0
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
+#define DG1_PCODE_STATUS 0x7E
+#define DG1_CHECK_UNCORE_INIT_STATUS 0x0
+#define DG1_UNCORE_INIT_COMPLETE 0x1
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 916ccd1c0e96..8b093525240d 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -543,3 +543,18 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
return ret ? ret : status;
#undef COND
}
+
+void intel_pcode_init(struct drm_i915_private *i915)
+{
+ int ret;
+
+ if (!IS_DGFX(i915))
+ return;
+
+ ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
+ DG1_CHECK_UNCORE_INIT_STATUS,
+ DG1_UNCORE_INIT_COMPLETE,
+ DG1_UNCORE_INIT_COMPLETE, 50);
+ if (ret)
+ drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
+}
diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
index 7fb95745a444..094c7b19c5d4 100644
--- a/drivers/gpu/drm/i915/intel_sideband.h
+++ b/drivers/gpu/drm/i915/intel_sideband.h
@@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
+void intel_pcode_init(struct drm_i915_private *i915);
+
#endif /* _INTEL_SIDEBAND_H */
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 12/28] drm/i915/dg1: Add DPLL macros for DG1
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (10 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 11/28] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 13/28] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
` (23 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Aditya Swarup <aditya.swarup@intel.com>
DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
DPLL2 and DPLL3 drive DDIC/DDID.
Introduce DG1_DPLL_CFCRx() helper macros to configure
DPLL registers.
Bspec: 50288, 50299
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 +++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 17 ++++++++++++++++-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 5d9a2bc371e7..205542fb8dc7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -154,6 +154,23 @@ enum intel_dpll_id {
* @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
*/
DPLL_ID_TGL_MGPLL6 = 8,
+
+ /**
+ * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
+ */
+ DPLL_ID_DG1_DPLL0 = 0,
+ /**
+ * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
+ */
+ DPLL_ID_DG1_DPLL1 = 1,
+ /**
+ * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
+ */
+ DPLL_ID_DG1_DPLL2 = 2,
+ /**
+ * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
+ */
+ DPLL_ID_DG1_DPLL3 = 3,
};
#define I915_NUM_PLLS 9
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bd64272f9844..7d0368c69069 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,7 +242,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
-#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
+#define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__))
+
/*
* Device info offset array based helpers for groups of registers with unevenly
@@ -10510,6 +10511,20 @@ enum skl_power_gate {
_TGL_DPLL1_CFGCR1, \
_TGL_TBTPLL_CFGCR1)
+#define _DG1_DPLL2_CFGCR0 0x16C284
+#define _DG1_DPLL3_CFGCR0 0x16C28C
+#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+ _TGL_DPLL1_CFGCR0, \
+ _DG1_DPLL2_CFGCR0, \
+ _DG1_DPLL3_CFGCR0)
+
+#define _DG1_DPLL2_CFGCR1 0x16C288
+#define _DG1_DPLL3_CFGCR1 0x16C290
+#define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+ _TGL_DPLL1_CFGCR1, \
+ _DG1_DPLL2_CFGCR1, \
+ _DG1_DPLL3_CFGCR1)
+
#define _DKL_PHY1_BASE 0x168000
#define _DKL_PHY2_BASE 0x169000
#define _DKL_PHY3_BASE 0x16A000
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 13/28] drm/i915/dg1: Add and setup DPLLs for DG1
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (11 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 12/28] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 14/28] drm/i915/dg1: Enable DPLL " Lucas De Marchi
` (22 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Aditya Swarup <aditya.swarup@intel.com>
Add entries for dg1 plls and setup dg1_pll_mgr to reuse icl callbacks.
Initial setup for shared dplls DPLL0/1 for DDIA/B and DPLL2/3 for
DDIC/D. Configure dpll cfgcrx registers to drive the plls on DG1.
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 41 +++++++++++++++++--
1 file changed, 37 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index aeb6ee395cce..25c6dca096ac 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3504,7 +3504,17 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
- if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
+ if (IS_DG1(dev_priv)) {
+ if (port == PORT_D || port == PORT_E) {
+ dpll_mask =
+ BIT(DPLL_ID_DG1_DPLL2) |
+ BIT(DPLL_ID_DG1_DPLL3);
+ } else {
+ dpll_mask =
+ BIT(DPLL_ID_DG1_DPLL0) |
+ BIT(DPLL_ID_DG1_DPLL1);
+ }
+ } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
dpll_mask =
BIT(DPLL_ID_EHL_DPLL4) |
BIT(DPLL_ID_ICL_DPLL1) |
@@ -3791,7 +3801,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
if (!(val & PLL_ENABLE))
goto out;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (IS_DG1(dev_priv)) {
+ hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
+ } else if (INTEL_GEN(dev_priv) >= 12) {
hw_state->cfgcr0 = intel_de_read(dev_priv,
TGL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = intel_de_read(dev_priv,
@@ -3844,7 +3857,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
const enum intel_dpll_id id = pll->info->id;
i915_reg_t cfgcr0_reg, cfgcr1_reg;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (IS_DG1(dev_priv)) {
+ cfgcr0_reg = DG1_DPLL_CFGCR0(id);
+ cfgcr1_reg = DG1_DPLL_CFGCR1(id);
+ } else if (INTEL_GEN(dev_priv) >= 12) {
cfgcr0_reg = TGL_DPLL_CFGCR0(id);
cfgcr1_reg = TGL_DPLL_CFGCR1(id);
} else {
@@ -4276,6 +4292,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info dg1_plls[] = {
+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 },
+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 },
+ { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
+ { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr dg1_pll_mgr = {
+ .dpll_info = dg1_plls,
+ .get_dplls = icl_get_dplls,
+ .put_dplls = icl_put_dplls,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -4289,7 +4320,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (IS_DG1(dev_priv))
+ dpll_mgr = &dg1_pll_mgr;
+ else if (INTEL_GEN(dev_priv) >= 12)
dpll_mgr = &tgl_pll_mgr;
else if (IS_ELKHARTLAKE(dev_priv))
dpll_mgr = &ehl_pll_mgr;
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 14/28] drm/i915/dg1: Enable DPLL for DG1
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (12 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 13/28] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 15/28] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
` (21 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Aditya Swarup <aditya.swarup@intel.com>
Add DG1 DPLL Enable register macro and use the macro to enable the
correct DPLL based on PLL id.
Bspec: 49443, 49206
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 ++++++++++++-------
drivers/gpu/drm/i915/i915_reg.h | 4 +++
2 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 25c6dca096ac..0c58d8012d32 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3833,12 +3833,14 @@ static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv))
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ else if (IS_ELKHARTLAKE(dev_priv) && pll->info->id == DPLL_ID_EHL_DPLL4)
enable_reg = MG_PLL_ENABLE(0);
- }
+ else
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
}
@@ -4036,10 +4038,12 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
static void combo_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv)) {
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ } else if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
enable_reg = MG_PLL_ENABLE(0);
/*
@@ -4049,6 +4053,8 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
*/
pll->wakeref = intel_display_power_get(dev_priv,
POWER_DOMAIN_DPLL_DC_OFF);
+ } else {
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
}
icl_pll_power_enable(dev_priv, pll, enable_reg);
@@ -4148,16 +4154,20 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
static void combo_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv)) {
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ } else if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
enable_reg = MG_PLL_ENABLE(0);
icl_pll_disable(dev_priv, pll, enable_reg);
intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
pll->wakeref);
return;
+ } else {
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
}
icl_pll_disable(dev_priv, pll, enable_reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7d0368c69069..57f7c48034e7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10297,6 +10297,10 @@ enum skl_power_gate {
#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
_MG_PLL2_ENABLE)
+/* DG1 PLL */
+#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+ _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
+
#define _MG_REFCLKIN_CTL_PORT1 0x16892C
#define _MG_REFCLKIN_CTL_PORT2 0x16992C
#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 15/28] drm/i915/dg1: add hpd interrupt handling
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (13 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 14/28] drm/i915/dg1: Enable DPLL " Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 16/28] drm/i915/dg1: invert HPD pins Lucas De Marchi
` (20 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
DG1 has one more combo phy port, no TC and all irq handling goes through
SDE, like for MCC.
v2: Also change intel_hpd_pin_default() to include DG1 mapping
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 3 +-
drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 8 +++
3 files changed, 61 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 80bcfff032e9..2cd022ee97a2 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -95,7 +95,8 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
* shold be HPD_PORT_{D,E} rather than {C,D}. Note that this differs
* from the behavior of both TGL+TGP and RKL+CMP.
*/
- if (IS_ROCKETLAKE(dev_priv) && HAS_PCH_TGP(dev_priv))
+ if (IS_DG1(dev_priv) ||
+ (IS_ROCKETLAKE(dev_priv) && HAS_PCH_TGP(dev_priv)))
return HPD_PORT_A + port - PORT_A;
switch (phy) {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1fa67700d8f4..e8bdc52c94bb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
[HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
};
+static const u32 hpd_dg1_sde[HPD_NUM_PINS] = {
+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A),
+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B),
+ [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C),
+ [HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D),
+};
+
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
{
struct i915_hotplug *hpd = &dev_priv->hotplug;
@@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
else
hpd->hpd = hpd_ilk;
- if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
+ if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
+ (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
return;
- if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
+ if (HAS_PCH_DG1(dev_priv))
+ hpd->pch_hpd = hpd_dg1_sde;
+ else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
hpd->pch_hpd = hpd_tgp;
else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
hpd->pch_hpd = hpd_icp;
@@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
}
}
+static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
+{
+ switch (pin) {
+ case HPD_PORT_A:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
+ case HPD_PORT_B:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
+ case HPD_PORT_D:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
+ case HPD_PORT_E:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
+ default:
+ return false;
+ }
+}
+
static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
@@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
u32 ddi_hotplug_trigger, tc_hotplug_trigger;
u32 pin_mask = 0, long_mask = 0;
bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
+ bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
- if (HAS_PCH_TGP(dev_priv)) {
+ if (HAS_PCH_DG1(dev_priv)) {
+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
+ ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect;
+ tc_hotplug_trigger = 0;
+ } else if (HAS_PCH_TGP(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
+ ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
} else if (HAS_PCH_JSP(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
+ ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
tc_hotplug_trigger = 0;
} else if (HAS_PCH_MCC(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
@@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
INTEL_PCH_TYPE(dev_priv));
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
+ ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
}
@@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
ddi_hotplug_trigger, dig_hotplug_reg,
dev_priv->hotplug.pch_hpd,
- icp_ddi_port_hotplug_long_detect);
+ ddi_port_hotplug_long_detect);
}
if (tc_hotplug_trigger) {
@@ -3145,6 +3179,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
TGP_DDI_HPD_ENABLE_MASK, 0);
}
+static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+ icp_hpd_irq_setup(dev_priv,
+ SDE_DDI_MASK_DG1, 0,
+ DG1_DDI_HPD_ENABLE_MASK, 0);
+}
+
static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug;
@@ -3533,7 +3574,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
- if (HAS_PCH_TGP(dev_priv))
+ if (HAS_PCH_DG1(dev_priv))
+ icp_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0);
+ else if (HAS_PCH_TGP(dev_priv))
icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
TGP_TC_HPD_ENABLE_MASK);
else if (HAS_PCH_JSP(dev_priv))
@@ -4049,7 +4092,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (I915_HAS_HOTPLUG(dev_priv))
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
} else {
- if (HAS_PCH_JSP(dev_priv))
+ if (HAS_PCH_DG1(dev_priv))
+ dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+ else if (HAS_PCH_JSP(dev_priv))
dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
else if (HAS_PCH_MCC(dev_priv))
dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 57f7c48034e7..6a853088a6e2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8220,6 +8220,10 @@ enum {
SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_C) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_B) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_A))
#define SDEISR _MMIO(0xc4000)
#define SDEIMR _MMIO(0xc4004)
@@ -8419,6 +8423,10 @@ enum {
#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
ICP_TC_HPD_ENABLE(PORT_TC5) | \
ICP_TC_HPD_ENABLE_MASK)
+#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
#define _PCH_DPLL_A 0xc6014
#define _PCH_DPLL_B 0xc6018
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 16/28] drm/i915/dg1: invert HPD pins
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (14 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 15/28] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 17/28] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
` (19 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Clinton A Taylor <clinton.a.taylor@intel.com>
HPD pins are inverted for DG1 platform.
Bspec: 49956
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++++
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e8bdc52c94bb..6225390edbb4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3181,6 +3181,10 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
+ intel_de_rmw(dev_priv, SOUTH_CHICKEN1, 0,
+ INVERT_DDIA_HPD | INVERT_DDIB_HPD |
+ INVERT_DDIC_HPD | INVERT_DDID_HPD);
+
icp_hpd_irq_setup(dev_priv,
SDE_DDI_MASK_DG1, 0,
DG1_DDI_HPD_ENABLE_MASK, 0);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6a853088a6e2..6b5dee1a82e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8687,6 +8687,10 @@ enum {
#define SOUTH_CHICKEN1 _MMIO(0xc2000)
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
#define FDIA_PHASE_SYNC_SHIFT_EN 18
+#define INVERT_DDID_HPD (1 << 18)
+#define INVERT_DDIC_HPD (1 << 17)
+#define INVERT_DDIB_HPD (1 << 16)
+#define INVERT_DDIA_HPD (1 << 15)
#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
#define FDI_BC_BIFURCATION_SELECT (1 << 12)
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 17/28] drm/i915/dg1: gmbus pin mapping
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (15 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 16/28] drm/i915/dg1: invert HPD pins Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 18/28] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
` (18 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
The values for VBT are currently not in BSpec. If we assume the latest
is ICL (like we did for TGL), then the mapping is wrong per VBT we can
currently parse.
From spec we have registers GPIO_CTL[1-4], so we should not do the 4->9
mapping as in ICL/TGL.
BSpec: 49311, 49945, 20124
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 4 +++-
drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +++++++++++++--
drivers/gpu/drm/i915/display/intel_hdmi.c | 9 ++++++++-
3 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 6593e2c38043..f1fc0c9bf9eb 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1599,7 +1599,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
const u8 *ddc_pin_map;
int n_entries;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
+ return vbt_pin;
+ } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
ddc_pin_map = icp_ddc_pin_map;
n_entries = ARRAY_SIZE(icp_ddc_pin_map);
} else if (HAS_PCH_CNP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index a8d119b6b45c..528e48658340 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -90,11 +90,20 @@ static const struct gmbus_pin gmbus_pins_icp[] = {
[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
};
+static const struct gmbus_pin gmbus_pins_dg1[] = {
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+ [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+};
+
/* pin is expected to be valid */
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ return &gmbus_pins_dg1[pin];
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
return &gmbus_pins_icp[pin];
else if (HAS_PCH_CNP(dev_priv))
return &gmbus_pins_cnp[pin];
@@ -113,7 +122,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
{
unsigned int size;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ size = ARRAY_SIZE(gmbus_pins_dg1);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
size = ARRAY_SIZE(gmbus_pins_icp);
else if (HAS_PCH_CNP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_cnp);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 864a1642e81c..42d62fcc7a91 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3113,6 +3113,11 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
return GMBUS_PIN_1_BXT + phy;
}
+static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+ return intel_port_to_phy(dev_priv, port) + 1;
+}
+
static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -3150,7 +3155,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
return ddc_pin;
}
- if (IS_ROCKETLAKE(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
+ else if (IS_ROCKETLAKE(dev_priv))
ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 18/28] drm/i915/dg1: Enable first 2 ports for DG1
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (16 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 17/28] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 19/28] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
` (17 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Aditya Swarup <aditya.swarup@intel.com>
Enable PORTS A and B for DG1 initially, the other ports still need more
plumbing code in order to be enabled.
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 84e2a17b5ecb..85104bcac942 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7230,6 +7230,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
+ else if (IS_DG1(dev_priv))
+ /* FIXME: Enable only two ports for now */
+ return phy <= PHY_B;
else if (IS_ROCKETLAKE(dev_priv))
return phy <= PHY_D;
else if (IS_ELKHARTLAKE(dev_priv))
@@ -7242,7 +7245,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_ROCKETLAKE(dev_priv) || IS_DG1(dev_priv))
return false;
else if (INTEL_GEN(dev_priv) >= 12)
return phy >= PHY_D && phy <= PHY_I;
@@ -16840,11 +16843,15 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
return;
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ /* FIXME: Enable only two ports for now */
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ } else if (IS_ROCKETLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
- intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
- intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
+ intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
+ intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
} else if (INTEL_GEN(dev_priv) >= 12) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 19/28] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (17 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 18/28] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-08 7:17 ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 20/28] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
` (16 subsequent siblings)
35 siblings, 1 reply; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the bspec
details for that bit tell us that it need only be set for PHY-A and
PHY-B. It also turns out that there isn't even an instance of the
PHY_MISC register for PHY-D on this platform. Let's extend the EHL/RKL
logic that conditionally skips PHY_MISC usage to DG1 as well.
Bspec: 50107
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 77b04bb3ec62..8604d4392e6a 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -189,7 +189,8 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
* other combo PHY's.
*/
if (IS_ELKHARTLAKE(i915) ||
- IS_ROCKETLAKE(i915))
+ IS_ROCKETLAKE(i915) ||
+ IS_DG1(i915))
return phy < PHY_C;
return true;
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [Intel-gfx] [PATCH v3 19/28] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 19/28] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
@ 2020-07-08 7:17 ` Srivatsa, Anusha
0 siblings, 0 replies; 46+ messages in thread
From: Srivatsa, Anusha @ 2020-07-08 7:17 UTC (permalink / raw)
To: De Marchi, Lucas, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Lucas De Marchi
> Sent: Thursday, July 2, 2020 5:24 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 19/28] drm/i915/dg1: Don't program
> PHY_MISC for PHY-C and PHY-D
>
> From: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the
> bspec details for that bit tell us that it need only be set for PHY-A and PHY-
> B. It also turns out that there isn't even an instance of the PHY_MISC
> register for PHY-D on this platform. Let's extend the EHL/RKL logic that
> conditionally skips PHY_MISC usage to DG1 as well.
>
> Bspec: 50107
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_combo_phy.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 77b04bb3ec62..8604d4392e6a 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -189,7 +189,8 @@ static bool has_phy_misc(struct drm_i915_private
> *i915, enum phy phy)
> * other combo PHY's.
> */
> if (IS_ELKHARTLAKE(i915) ||
> - IS_ROCKETLAKE(i915))
> + IS_ROCKETLAKE(i915) ||
> + IS_DG1(i915))
> return phy < PHY_C;
>
> return true;
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v3 20/28] drm/i915/dg1: Update comp master/slave relationships for PHYs
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (18 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 19/28] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-08 7:51 ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 21/28] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
` (15 subsequent siblings)
35 siblings, 1 reply; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
As with RKL, DG1's PHY C acts as a comp master for PHY D.
Bspec: 49291
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 8604d4392e6a..2fad4871d4e6 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -243,14 +243,14 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
*
* ICL,TGL:
* A(master) -> B(slave), C(slave)
- * RKL:
+ * RKL,DG1:
* A(master) -> B(slave)
* C(master) -> D(slave)
*
* We must set the IREFGEN bit for any PHY acting as a master
* to another PHY.
*/
- if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
+ if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C)
return true;
return phy == PHY_A;
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [Intel-gfx] [PATCH v3 20/28] drm/i915/dg1: Update comp master/slave relationships for PHYs
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 20/28] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
@ 2020-07-08 7:51 ` Srivatsa, Anusha
0 siblings, 0 replies; 46+ messages in thread
From: Srivatsa, Anusha @ 2020-07-08 7:51 UTC (permalink / raw)
To: De Marchi, Lucas, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Lucas De Marchi
> Sent: Thursday, July 2, 2020 5:24 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 20/28] drm/i915/dg1: Update comp
> master/slave relationships for PHYs
>
> From: Matt Roper <matthew.d.roper@intel.com>
>
> As with RKL, DG1's PHY C acts as a comp master for PHY D.
>
> Bspec: 49291
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 8604d4392e6a..2fad4871d4e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -243,14 +243,14 @@ static bool phy_is_master(struct
> drm_i915_private *dev_priv, enum phy phy)
> *
> * ICL,TGL:
> * A(master) -> B(slave), C(slave)
> - * RKL:
> + * RKL,DG1:
> * A(master) -> B(slave)
> * C(master) -> D(slave)
> *
> * We must set the IREFGEN bit for any PHY acting as a master
> * to another PHY.
> */
> - if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
> + if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy ==
> PHY_C)
> return true;
>
> return phy == PHY_A;
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v3 21/28] drm/i915/dg1: Update voltage swing tables for DP
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (19 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 20/28] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-08 10:23 ` Srivatsa, Anusha
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 22/28] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
` (14 subsequent siblings)
35 siblings, 1 reply; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
DG1's vswing tables are the same for eDP and HDMI but have slight
differences from ICL/TGL for DP.
Bspec: 49291
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 34 ++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 025d4052f6f8..9c230f532bbe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
+static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
+ { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
+ { 0xC, 0x60, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
+};
+
+static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
+ { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
+ { 0xC, 0x58, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
+};
+
struct icl_mg_phy_ddi_buf_trans {
u32 cri_txdeemph_override_11_6;
u32 cri_txdeemph_override_5_0;
@@ -993,6 +1021,12 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
return icl_combo_phy_ddi_translations_edp_hbr2;
+ } else if (IS_DG1(dev_priv) && rate > 270000) {
+ *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2);
+ return dg1_combo_phy_ddi_translations_dp_hbr2;
+ } else if (IS_DG1(dev_priv)) {
+ *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr);
+ return dg1_combo_phy_ddi_translations_dp_hbr;
}
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [Intel-gfx] [PATCH v3 21/28] drm/i915/dg1: Update voltage swing tables for DP
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 21/28] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
@ 2020-07-08 10:23 ` Srivatsa, Anusha
0 siblings, 0 replies; 46+ messages in thread
From: Srivatsa, Anusha @ 2020-07-08 10:23 UTC (permalink / raw)
To: De Marchi, Lucas, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Lucas De Marchi
> Sent: Thursday, July 2, 2020 5:24 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 21/28] drm/i915/dg1: Update voltage swing
> tables for DP
>
> From: Matt Roper <matthew.d.roper@intel.com>
>
> DG1's vswing tables are the same for eDP and HDMI but have slight
> differences from ICL/TGL for DP.
>
> Bspec: 49291
> Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 34 ++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 025d4052f6f8..9c230f532bbe 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans
> ehl_combo_phy_ddi_translations_dp[] = {
> { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> };
>
> +static const struct cnl_ddi_buf_trans
> dg1_combo_phy_ddi_translations_dp_hbr[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */
> + { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
> + { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
> + { 0xC, 0x60, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
> + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> +};
> +
> +static const struct cnl_ddi_buf_trans
> dg1_combo_phy_ddi_translations_dp_hbr2[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */
> + { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
> + { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
> + { 0xC, 0x58, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> +};
From the bSpec page, the hbr2 values above are incorrect in more than one place.
Anusha
> +
> struct icl_mg_phy_ddi_buf_trans {
> u32 cri_txdeemph_override_11_6;
> u32 cri_txdeemph_override_5_0;
> @@ -993,6 +1021,12 @@ icl_get_combo_buf_trans(struct drm_i915_private
> *dev_priv, int type, int rate,
> } else if (type == INTEL_OUTPUT_EDP && dev_priv-
> >vbt.edp.low_vswing) {
> *n_entries =
> ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> return icl_combo_phy_ddi_translations_edp_hbr2;
> + } else if (IS_DG1(dev_priv) && rate > 270000) {
> + *n_entries =
> ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2);
> + return dg1_combo_phy_ddi_translations_dp_hbr2;
> + } else if (IS_DG1(dev_priv)) {
> + *n_entries =
> ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr);
> + return dg1_combo_phy_ddi_translations_dp_hbr;
> }
>
> *n_entries =
> ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v3 22/28] drm/i915/dg1: provide port/phy mapping for vbt
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (20 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 21/28] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 23/28] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
` (13 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
As with RKL, DG1's VBT outputs are indexed according to PHY rather than
DDI.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index f1fc0c9bf9eb..1f63e734db8c 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1670,7 +1670,7 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
};
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
ARRAY_SIZE(rkl_port_mapping[0]),
rkl_port_mapping,
@@ -2635,10 +2635,12 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
aux_ch = AUX_CH_B;
break;
case DP_AUX_C:
- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
+ aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
+ AUX_CH_D : AUX_CH_C;
break;
case DP_AUX_D:
- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
+ aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
+ AUX_CH_E : AUX_CH_D;
break;
case DP_AUX_E:
aux_ch = AUX_CH_E;
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 23/28] drm/i915/dg1: map/unmap pll clocks
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (21 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 22/28] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 24/28] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
` (12 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
single macro that chooses the correct register according to the phy
being accessed, use the correct bitfields for each pll/phy and implement
separate functions for DG1 since it doesn't share much with ICL/TGL
anymore.
The previous values were correct for PHY A and B since they were using
the same register as before and the bitfields were matching.
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 92 +++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_display.c | 25 +++++-
drivers/gpu/drm/i915/i915_reg.h | 15 ++++
3 files changed, 128 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9c230f532bbe..ee7164800c6d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2814,6 +2814,38 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
return 0;
}
+static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ u32 val;
+
+ /*
+ * If we fail this, something went very wrong: first 2 PLLs should be
+ * used by first 2 phys and last 2 PLLs by last phys
+ */
+ if (WARN_ON((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
+ (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
+ return;
+
+ mutex_lock(&dev_priv->dpll.lock);
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+ WARN_ON((val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
+
+ val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+ intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+
+ val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+
+ mutex_unlock(&dev_priv->dpll.lock);
+}
+
static void icl_map_plls_to_ports(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -2851,6 +2883,19 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
mutex_unlock(&dev_priv->dpll.lock);
}
+static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+ mutex_lock(&dev_priv->dpll.lock);
+
+ intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
+ DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+
+ mutex_unlock(&dev_priv->dpll.lock);
+}
+
static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2866,6 +2911,40 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
mutex_unlock(&dev_priv->dpll.lock);
}
+static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
+ u32 port_mask, bool ddi_clk_needed)
+{
+ enum port port;
+ u32 val;
+
+ for_each_port_masked(port, port_mask) {
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+ bool ddi_clk_off;
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+ ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+
+ if (ddi_clk_needed == !ddi_clk_off)
+ continue;
+
+ /*
+ * Punt on the case now where clock is gated, but it would
+ * be needed by the port. Something else is really broken then.
+ */
+ if (ddi_clk_needed) {
+ WARN(1, "ddi_clk_needed=%u ddi_clk_off=%u phy=%u\n",
+ ddi_clk_needed, ddi_clk_off, phy);
+ continue;
+ }
+
+ DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
+ phy_name(phy));
+
+ val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+ }
+}
+
static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
u32 port_mask, bool ddi_clk_needed)
{
@@ -2948,7 +3027,10 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
ddi_clk_needed = false;
}
- icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
+ if (IS_DG1(dev_priv))
+ dg1_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
+ else
+ icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
}
static void intel_ddi_clk_select(struct intel_encoder *encoder,
@@ -3473,7 +3555,9 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state,
drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_DG1(dev_priv))
+ dg1_map_plls_to_ports(encoder, crtc_state);
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_map_plls_to_ports(encoder, crtc_state);
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -3659,7 +3743,9 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
old_conn_state);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_DG1(dev_priv))
+ dg1_unmap_plls_to_ports(encoder);
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_unmap_plls_to_ports(encoder);
if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 85104bcac942..f5d834fa82eb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10780,6 +10780,27 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
return 0;
}
+static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+ struct intel_crtc_state *pipe_config)
+{
+ enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+ enum intel_dpll_id id;
+ u32 val;
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy))
+ & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy);
+
+ if (WARN_ON(id > DPLL_ID_DG1_DPLL3))
+ return;
+
+ pipe_config->icl_port_dplls[port_dpll_id].pll =
+ intel_get_shared_dpll_by_id(dev_priv, id);
+
+ icl_set_active_port_dpll(pipe_config, port_dpll_id);
+}
+
static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
struct intel_crtc_state *pipe_config)
{
@@ -11079,7 +11100,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
}
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_DG1(dev_priv))
+ dg1_get_ddi_pll(dev_priv, port, pipe_config);
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_CANNONLAKE(dev_priv))
cnl_get_ddi_pll(dev_priv, port, pipe_config);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6b5dee1a82e1..591b30eeb7fd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -230,12 +230,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
+#define _PHY(phy, a, b) _PICK_EVEN(phy, a, b)
#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
+#define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))
#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
@@ -10281,6 +10283,7 @@ enum skl_power_gate {
#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
+/* ICL Clocks */
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
@@ -10290,6 +10293,18 @@ enum skl_power_gate {
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+/* DG1 Clocks */
+#define _DG1_DPCLKA_CFGCR0 0x164280
+#define _DG1_DPCLKA1_CFGCR0 0x16C280
+#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
+ _DG1_DPCLKA_CFGCR0, \
+ _DG1_DPCLKA1_CFGCR0)
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << (10 + ((phy) % 2)))
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << (((phy) % 2) * 2))
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (((pll) % 2) << (((phy) % 2)) * 2)
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \
+ ((((val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2)))
+
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
#define DPLL1_ENABLE 0x46014
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 24/28] drm/i915/dg1: enable PORT C/D aka D/E
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (22 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 23/28] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 25/28] drm/i915/dg1: Load DMC Lucas De Marchi
` (11 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
For DG1 we have a little of mix up wrt to DDI/port names and indexes.
Bspec refers to the ports as DDIA, DDIB, DDI USBC1 and DDI USBC2
(besides the DDIA, DDIB, DDIC, DDID), but the previous naming is the
most unambiguous one. This means that for any register on Display Engine
we should use the index of A, B, D and E. However in some places this is
not true:
- VBT: uses C and D and have to be mapped to D/E
- IO/Combo: uses C and D, but we already differentiate those when
we created the phy vs port distinction.
Ths additional mapping for VBT and phy are already covered in previous
patches, so now we can initialize the DDI as D/E.
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f5d834fa82eb..fdc46dd5e8fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7230,10 +7230,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
- else if (IS_DG1(dev_priv))
- /* FIXME: Enable only two ports for now */
- return phy <= PHY_B;
- else if (IS_ROCKETLAKE(dev_priv))
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return phy <= PHY_D;
else if (IS_ELKHARTLAKE(dev_priv))
return phy <= PHY_C;
@@ -7257,7 +7254,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if (IS_ROCKETLAKE(i915) && port >= PORT_D)
+ if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_D)
return (enum phy)port - 1;
else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
return PHY_A;
@@ -16867,9 +16864,18 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
return;
if (IS_DG1(dev_priv)) {
- /* FIXME: Enable only two ports for now */
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
+
+ /*
+ * Bspec lists the ports as A, B, C (USBC1) and D (USBC2).
+ * However from the Display Engine perspective all registers are
+ * actually wired to handle C and D as offsets of D/E. Instead
+ * of fighting all our macros for handling them specially for
+ * DG1, just call them D/E
+ */
+ intel_ddi_init(dev_priv, PORT_D);
+ intel_ddi_init(dev_priv, PORT_E);
} else if (IS_ROCKETLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 25/28] drm/i915/dg1: Load DMC
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (23 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 24/28] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 26/28] drm/i915/rkl: Add initial workarounds Lucas De Marchi
` (10 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Matt Atwood <matthew.s.atwood@intel.com>
Add support to load DMC v2.0.2 on DG1
While we're at it, tweak the TGL and RKL firmware size definition to
follow the convention used in previous platforms. Remove obsolete
commenting.
Bpec: 49230
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_csr.c | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index f22a7645c249..ccf13ea627d7 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -38,15 +38,19 @@
* low-power state and comes back to normal.
*/
-#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
+#define DG1_CSR_PATH "i915/dg1_dmc_ver2_02.bin"
+#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
+#define DG1_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
+MODULE_FIRMWARE(DG1_CSR_PATH);
#define RKL_CSR_PATH "i915/rkl_dmc_ver2_01.bin"
#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
+#define RKL_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
MODULE_FIRMWARE(RKL_CSR_PATH);
#define TGL_CSR_PATH "i915/tgl_dmc_ver2_06.bin"
#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 6)
-#define TGL_CSR_MAX_FW_SIZE 0x6000
+#define TGL_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
MODULE_FIRMWARE(TGL_CSR_PATH);
#define ICL_CSR_PATH "i915/icl_dmc_ver1_09.bin"
@@ -686,15 +690,18 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
*/
intel_csr_runtime_pm_get(dev_priv);
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ csr->fw_path = DG1_CSR_PATH;
+ csr->required_version = DG1_CSR_VERSION_REQUIRED;
+ csr->max_fw_size = DG1_CSR_MAX_FW_SIZE;
+ } else if (IS_ROCKETLAKE(dev_priv)) {
csr->fw_path = RKL_CSR_PATH;
csr->required_version = RKL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ csr->max_fw_size = RKL_CSR_MAX_FW_SIZE;
} else if (INTEL_GEN(dev_priv) >= 12) {
csr->fw_path = TGL_CSR_PATH;
csr->required_version = TGL_CSR_VERSION_REQUIRED;
- /* Allow to load fw via parameter using the last known size */
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ csr->max_fw_size = TGL_CSR_MAX_FW_SIZE;
} else if (IS_GEN(dev_priv, 11)) {
csr->fw_path = ICL_CSR_PATH;
csr->required_version = ICL_CSR_VERSION_REQUIRED;
--
2.26.2
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 26/28] drm/i915/rkl: Add initial workarounds
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (24 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 25/28] drm/i915/dg1: Load DMC Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 27/28] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
` (9 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
RKL and TGL share some general gen12 workarounds, but each platform also
has its own platform-specific workarounds.
v2:
- Add Wa_1604555607 for RKL. This makes RKL's ctx WA list identical to
TGL's, so we'll have both functions call the tgl_ function for now;
this workaround isn't listed for DG1 so we don't want to add it to
the general gen12_ function.
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +++++++++++++--------
2 files changed, 59 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index d03860fef2d7..c26ca029fc0a 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2843,8 +2843,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- /* Wa_14010477008:tgl[a0..c0] */
- if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
+ /* Wa_14010477008:tgl[a0..c0],rkl[all] */
+ if (IS_ROCKETLAKE(dev_priv) ||
+ IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
return false;
return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2da366821dda..741710ca2b9a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -596,8 +596,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
}
-static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
- struct i915_wa_list *wal)
+static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
{
/*
* Wa_1409142259:tgl
@@ -607,12 +607,28 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
* Wa_1409207793:tgl
* Wa_1409178076:tgl
* Wa_1408979724:tgl
+ * Wa_14010443199:rkl
+ * Wa_14010698770:rkl
*/
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+ /* WaDisableGPGPUMidThreadPreemption:gen12 */
+ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
+ GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+ GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
+}
+
+static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
+{
+ gen12_ctx_workarounds_init(engine, wal);
+
/*
- * Wa_1604555607:gen12 and Wa_1608008084:gen12
+ * Wa_1604555607:tgl,rkl
+ *
+ * Note that the implementation of this workaround is further modified
+ * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
* FF_MODE2 register will return the wrong value when read. The default
* value for this register is zero for all fields and there are no bit
* masks. So instead of doing a RMW we should just write the GS Timer
@@ -623,11 +639,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128,
0);
-
- /* WaDisableGPGPUMidThreadPreemption:tgl */
- WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
- GEN9_PREEMPT_GPGPU_LEVEL_MASK,
- GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
}
static void
@@ -642,8 +653,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_GEN(i915, 12))
+ if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
tgl_ctx_workarounds_init(engine, wal);
+ else if (IS_GEN(i915, 12))
+ gen12_ctx_workarounds_init(engine, wal);
else if (IS_GEN(i915, 11))
icl_ctx_workarounds_init(engine, wal);
else if (IS_CANNONLAKE(i915))
@@ -1176,9 +1189,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
}
static void
-tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+gen12_gt_workarounds_init(struct drm_i915_private *i915,
+ struct i915_wa_list *wal)
{
wa_init_mcr(i915, wal);
+}
+
+static void
+tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ gen12_gt_workarounds_init(i915, wal);
/* Wa_1409420604:tgl */
if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
@@ -1196,8 +1216,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_GEN(i915, 12))
+ if (IS_TIGERLAKE(i915))
tgl_gt_workarounds_init(i915, wal);
+ else if (IS_GEN(i915, 12))
+ gen12_gt_workarounds_init(i915, wal);
else if (IS_GEN(i915, 11))
icl_gt_workarounds_init(i915, wal);
else if (IS_CANNONLAKE(i915))
@@ -1629,18 +1651,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN9_CTX_PREEMPT_REG,
GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
- /*
- * Wa_1607030317:tgl
- * Wa_1607186500:tgl
- * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2
- * of then says it is fixed on B0 the other one says it is
- * permanent
- */
- wa_masked_en(wal,
- GEN6_RC_SLEEP_PSMI_CONTROL,
- GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
- GEN8_RC_SEMA_IDLE_MSG_DISABLE);
-
/*
* Wa_1606679103:tgl
* (see also Wa_1606682166:icl)
@@ -1659,24 +1669,38 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
VSUNIT_CLKGATE_DIS_TGL);
}
- if (IS_TIGERLAKE(i915)) {
- /* Wa_1606931601:tgl */
+ if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /* Wa_1606931601:tgl,rkl */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
- /* Wa_1409804808:tgl */
+ /* Wa_1409804808:tgl,rkl */
wa_masked_en(wal, GEN7_ROW_CHICKEN2,
GEN12_PUSH_CONST_DEREF_HOLD_DIS);
- /* Wa_1606700617:tgl */
- wa_masked_en(wal,
- GEN9_CS_DEBUG_MODE1,
- FF_DOP_CLOCK_GATE_DISABLE);
-
/*
* Wa_1409085225:tgl
- * Wa_14010229206:tgl
+ * Wa_14010229206:tgl,rkl
*/
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
+
+ /*
+ * Wa_1607030317:tgl
+ * Wa_1607186500:tgl
+ * Wa_1607297627:tgl,rkl there are multiple entries for this
+ * WA in the BSpec; some indicate this is an A0-only WA,
+ * others indicate it applies to all steppings.
+ */
+ wa_masked_en(wal,
+ GEN6_RC_SLEEP_PSMI_CONTROL,
+ GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+ GEN8_RC_SEMA_IDLE_MSG_DISABLE);
+ }
+
+ if (IS_TIGERLAKE(i915)) {
+ /* Wa_1606700617:tgl */
+ wa_masked_en(wal,
+ GEN9_CS_DEBUG_MODE1,
+ FF_DOP_CLOCK_GATE_DISABLE);
}
if (IS_GEN(i915, 11)) {
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 27/28] drm/i915/dg1: Add initial DG1 workarounds
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (25 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 26/28] drm/i915/rkl: Add initial workarounds Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 28/28] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
` (8 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Stuart Summers <stuart.summers@intel.com>
DG1 shares some workarounds with TGL and RKL and also has some
additional workarounds of its own.
Media power gating should not be applied so we just set it to
nop_init_clock_gating().
BSpec: 53508
v2: Also add Wa_16011227922
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../drm/i915/display/intel_display_power.c | 5 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 4 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 91 ++++++++++++++++---
drivers/gpu/drm/i915/i915_pci.c | 2 +
drivers/gpu/drm/i915/i915_reg.h | 10 +-
drivers/gpu/drm/i915/intel_pm.c | 17 +++-
6 files changed, 108 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3dc14a9ee00e..7ff9c6d5a363 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5462,8 +5462,9 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
int config, i;
- if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
- /* Wa_1409767108: tgl */
+ if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
+ /* Wa_1409767108:tgl,dg1 */
table = wa_1409767108_buddy_page_masks;
else
table = tgl_buddy_page_masks;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index c26ca029fc0a..d03a239e6977 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2843,8 +2843,8 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- /* Wa_14010477008:tgl[a0..c0],rkl[all] */
- if (IS_ROCKETLAKE(dev_priv) ||
+ /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
+ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
return false;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 741710ca2b9a..04abde1d3bf9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -641,6 +641,20 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
0);
}
+static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
+{
+ gen12_ctx_workarounds_init(engine, wal);
+
+ /* Wa_1409044764 */
+ WA_CLR_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN);
+
+ /* Wa_22010493298 */
+ WA_SET_BIT_MASKED(HIZ_CHICKEN,
+ DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
+}
+
static void
__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
struct i915_wa_list *wal,
@@ -653,7 +667,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
+ if (IS_DG1(i915))
+ dg1_ctx_workarounds_init(engine, wal);
+ else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
tgl_ctx_workarounds_init(engine, wal);
else if (IS_GEN(i915, 12))
gen12_ctx_workarounds_init(engine, wal);
@@ -1213,10 +1229,30 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
}
+static void
+dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ gen12_gt_workarounds_init(i915, wal);
+
+ /* Wa_1607087056:dg1 */
+ if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
+ wa_write_or(wal,
+ SLICE_UNIT_LEVEL_CLKGATE,
+ L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
+
+ /* Wa_1409420604:dg1 */
+ if (IS_DG1(i915))
+ wa_write_or(wal,
+ SUBSLICE_UNIT_LEVEL_CLKGATE2,
+ CPSSUNIT_CLKGATE_DIS);
+}
+
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_TIGERLAKE(i915))
+ if (IS_DG1(i915))
+ dg1_gt_workarounds_init(i915, wal);
+ else if (IS_TIGERLAKE(i915))
tgl_gt_workarounds_init(i915, wal);
else if (IS_GEN(i915, 12))
gen12_gt_workarounds_init(i915, wal);
@@ -1581,6 +1617,20 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
}
}
+static void dg1_whitelist_build(struct intel_engine_cs *engine)
+{
+ struct i915_wa_list *w = &engine->whitelist;
+
+ tgl_whitelist_build(engine);
+
+ /* GEN:BUG:1409280441:dg1 */
+ if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&
+ (engine->class == RENDER_CLASS ||
+ engine->class == COPY_ENGINE_CLASS))
+ whitelist_reg_ext(w, RING_ID(engine->mmio_base),
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
+}
+
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
@@ -1588,7 +1638,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
wa_init_start(w, "whitelist", engine->name);
- if (IS_GEN(i915, 12))
+ if (IS_DG1(i915))
+ dg1_whitelist_build(engine);
+ else if (IS_GEN(i915, 12))
tgl_whitelist_build(engine);
else if (IS_GEN(i915, 11))
icl_whitelist_build(engine);
@@ -1642,15 +1694,18 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+ if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
/*
- * Wa_1607138336:tgl
- * Wa_1607063988:tgl
+ * Wa_1607138336:tgl[a0],dg1[a0]
+ * Wa_1607063988:tgl[a0],dg1[a0]
*/
wa_write_or(wal,
GEN9_CTX_PREEMPT_REG,
GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
+ }
+ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
/*
* Wa_1606679103:tgl
* (see also Wa_1606682166:icl)
@@ -1665,30 +1720,40 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
/* Wa_1408615072:tgl */
+ }
+
+ if (IS_DG1(i915) || IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+ /* Wa_1408615072:tgl[a0],dg1 */
wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
VSUNIT_CLKGATE_DIS_TGL);
}
- if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
- /* Wa_1606931601:tgl,rkl */
+ if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /* Wa_1606931601:tgl,rkl,dg1 */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
+ }
- /* Wa_1409804808:tgl,rkl */
+ if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /* Wa_1409804808:tgl,rkl,dg1[a0] */
wa_masked_en(wal, GEN7_ROW_CHICKEN2,
GEN12_PUSH_CONST_DEREF_HOLD_DIS);
/*
* Wa_1409085225:tgl
- * Wa_14010229206:tgl,rkl
+ * Wa_14010229206:tgl,rkl,dg1[a0]
*/
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
/*
* Wa_1607030317:tgl
* Wa_1607186500:tgl
- * Wa_1607297627:tgl,rkl there are multiple entries for this
- * WA in the BSpec; some indicate this is an A0-only WA,
- * others indicate it applies to all steppings.
+ * Wa_1607297627:tgl,rkl,dg1[a0]
+ *
+ * On TGL and RKL there are multiple entries for this WA in the
+ * BSpec; some indicate this is an A0-only WA, others indicate
+ * it applies to all steppings so we trust the "all steppings."
+ * For DG1 this only applies to A0.
*/
wa_masked_en(wal,
GEN6_RC_SLEEP_PSMI_CONTROL,
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8cae64adbb23..d515468bbb21 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -908,6 +908,8 @@ static const struct intel_device_info dg1_info = {
.engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
BIT(VCS0) | BIT(VCS2),
+ /* Wa_16011227922 */
+ .ppgtt_size = 47,
};
#undef GEN
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 591b30eeb7fd..b6907a7c7f6e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2520,6 +2520,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
+#define RING_ID(base) _MMIO((base) + 0x8c)
#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
#define RESET_CTL_CAT_ERROR REG_BIT(2)
@@ -4132,6 +4133,7 @@ enum {
#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
#define TGL_VRH_GATING_DIS REG_BIT(31)
+#define DPT_GATING_DIS REG_BIT(22)
#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
#define BXT_GMBUS_GATING_DIS (1 << 14)
@@ -8011,12 +8013,14 @@ enum {
#define GEN8_L3CNTLREG _MMIO(0x7034)
#define GEN8_ERRDETBCTRL (1 << 9)
-#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
- #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
- #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9)
+#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
+#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
+#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
+#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
#define HIZ_CHICKEN _MMIO(0x7018)
# define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
+# define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE (1 << 14)
# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3)
#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 565a2b9da3b3..e685d6bbd609 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7132,6 +7132,19 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
0, DFR_DISABLE);
}
+static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ /*
+ * As opposed to TGL, we should not touch the registers for media power
+ * gating
+ */
+
+ /* Wa_14010096844:dg1[a0] */
+ if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
+ I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
+ DPT_GATING_DIS);
+}
+
static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
{
if (!HAS_PCH_CNP(dev_priv))
@@ -7508,7 +7521,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 12))
+ if (IS_DG1(dev_priv))
+ dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+ else if (IS_GEN(dev_priv, 12))
dev_priv->display.init_clock_gating = tgl_init_clock_gating;
else if (IS_GEN(dev_priv, 11))
dev_priv->display.init_clock_gating = icl_init_clock_gating;
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v3 28/28] drm/i915/dg1: DG1 does not support DC6
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (26 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 27/28] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
@ 2020-07-01 23:53 ` Lucas De Marchi
2020-07-02 0:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev3) Patchwork
` (7 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Lucas De Marchi @ 2020-07-01 23:53 UTC (permalink / raw)
To: intel-gfx
From: Anshuman Gupta <anshuman.gupta@intel.com>
DC6 is not supported on DG1, so change the allowed DC mask for DG1.
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7ff9c6d5a363..fff3a1d68678 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4689,7 +4689,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
int max_dc;
if (INTEL_GEN(dev_priv) >= 12) {
- max_dc = 4;
+ if (IS_DG1(dev_priv))
+ max_dc = 3;
+ else
+ max_dc = 4;
/*
* DC9 has a separate HW flow from the rest of the DC states,
* not depending on the DMC firmware. It's needed by system
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev3)
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (27 preceding siblings ...)
2020-07-01 23:53 ` [Intel-gfx] [PATCH v3 28/28] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
@ 2020-07-02 0:13 ` Patchwork
2020-07-02 0:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2020-07-02 0:13 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DG1 (rev3)
URL : https://patchwork.freedesktop.org/series/77496/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
988d01bfbd82 drm/i915: Add has_master_unit_irq flag
241025556ca5 drm/i915/dg1: add initial DG-1 definitions
-:41: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#41: FILE: drivers/gpu/drm/i915/i915_drv.h:1565:
+#define IS_DG1_REVID(p, since, until) \
+ (IS_DG1(p) && IS_REVID(p, since, until))
total: 0 errors, 0 warnings, 1 checks, 53 lines checked
c6bda5d540fd drm/i915/dg1: Add DG1 PCI IDs
e24161cc3641 drm/i915/dg1: add support for the master unit interrupt
6a75112b7aed drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
c34b0b236cf6 drm/i915/dg1: Add fake PCH
cf65ad570c8c drm/i915/dg1: Initialize RAWCLK properly
fedac7296bd4 drm/i915/dg1: Define MOCS table for DG1
322b9085eff2 drm/i915/dg1: Add DG1 power wells
5286f7943bfa drm/i915/dg1: Increase mmio size to 4MB
4aa9f50249e2 drm/i915/dg1: Wait for pcode/uncore handshake at startup
c62a0b547629 drm/i915/dg1: Add DPLL macros for DG1
82d28e83c02c drm/i915/dg1: Add and setup DPLLs for DG1
c1bd97f322b5 drm/i915/dg1: Enable DPLL for DG1
29d541db7fa4 drm/i915/dg1: add hpd interrupt handling
bebd570390ca drm/i915/dg1: invert HPD pins
dc4378f76bda drm/i915/dg1: gmbus pin mapping
28762e8057ef drm/i915/dg1: Enable first 2 ports for DG1
d9fee22a3149 drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
e9d9d678ccbb drm/i915/dg1: Update comp master/slave relationships for PHYs
b94b0daa426b drm/i915/dg1: Update voltage swing tables for DP
f3a63ae610cb drm/i915/dg1: provide port/phy mapping for vbt
6d2de4a643ed drm/i915/dg1: map/unmap pll clocks
-:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects?
#244: FILE: drivers/gpu/drm/i915/i915_reg.h:10305:
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \
+ ((((val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2)))
total: 0 errors, 0 warnings, 1 checks, 204 lines checked
0b374a4ce084 drm/i915/dg1: enable PORT C/D aka D/E
f4b22e8c57b9 drm/i915/dg1: Load DMC
352b53d3a545 drm/i915/rkl: Add initial workarounds
52c58ad484ed drm/i915/dg1: Add initial DG1 workarounds
9f3c06617494 drm/i915/dg1: DG1 does not support DC6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce DG1 (rev3)
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (28 preceding siblings ...)
2020-07-02 0:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev3) Patchwork
@ 2020-07-02 0:14 ` Patchwork
2020-07-02 0:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2020-07-02 0:14 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DG1 (rev3)
URL : https://patchwork.freedesktop.org/series/77496/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1223:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1226:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1229:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1232:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2267:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2268:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion
+drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion
+drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce DG1 (rev3)
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (29 preceding siblings ...)
2020-07-02 0:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-07-02 0:37 ` Patchwork
2020-07-02 4:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2020-07-02 0:37 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DG1 (rev3)
URL : https://patchwork.freedesktop.org/series/77496/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8689 -> Patchwork_18063
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/index.html
Known issues
------------
Here are the changes found in Patchwork_18063 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
#### Possible fixes ####
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][5] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/fi-kbl-x1275/igt@kms_busy@basic@flip.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92]) -> [DMESG-WARN][8] ([i915#62] / [i915#92] / [i915#95]) +7 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][10] ([i915#62] / [i915#92]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (43 -> 37)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8689 -> Patchwork_18063
CI-20190529: 20190529
CI_DRM_8689: 5be0c5eb5635e500c571bea544c850d54d7d4d47 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5719: 54731f017df8660f29cc8f5db0b570239729e808 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18063: 9f3c06617494d353e430dd4cc5974579417955b9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9f3c06617494 drm/i915/dg1: DG1 does not support DC6
52c58ad484ed drm/i915/dg1: Add initial DG1 workarounds
352b53d3a545 drm/i915/rkl: Add initial workarounds
f4b22e8c57b9 drm/i915/dg1: Load DMC
0b374a4ce084 drm/i915/dg1: enable PORT C/D aka D/E
6d2de4a643ed drm/i915/dg1: map/unmap pll clocks
f3a63ae610cb drm/i915/dg1: provide port/phy mapping for vbt
b94b0daa426b drm/i915/dg1: Update voltage swing tables for DP
e9d9d678ccbb drm/i915/dg1: Update comp master/slave relationships for PHYs
d9fee22a3149 drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
28762e8057ef drm/i915/dg1: Enable first 2 ports for DG1
dc4378f76bda drm/i915/dg1: gmbus pin mapping
bebd570390ca drm/i915/dg1: invert HPD pins
29d541db7fa4 drm/i915/dg1: add hpd interrupt handling
c1bd97f322b5 drm/i915/dg1: Enable DPLL for DG1
82d28e83c02c drm/i915/dg1: Add and setup DPLLs for DG1
c62a0b547629 drm/i915/dg1: Add DPLL macros for DG1
4aa9f50249e2 drm/i915/dg1: Wait for pcode/uncore handshake at startup
5286f7943bfa drm/i915/dg1: Increase mmio size to 4MB
322b9085eff2 drm/i915/dg1: Add DG1 power wells
fedac7296bd4 drm/i915/dg1: Define MOCS table for DG1
cf65ad570c8c drm/i915/dg1: Initialize RAWCLK properly
c34b0b236cf6 drm/i915/dg1: Add fake PCH
6a75112b7aed drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
e24161cc3641 drm/i915/dg1: add support for the master unit interrupt
c6bda5d540fd drm/i915/dg1: Add DG1 PCI IDs
241025556ca5 drm/i915/dg1: add initial DG-1 definitions
988d01bfbd82 drm/i915: Add has_master_unit_irq flag
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce DG1 (rev3)
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (30 preceding siblings ...)
2020-07-02 0:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-07-02 4:44 ` Patchwork
2020-07-02 7:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev4) Patchwork
` (3 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2020-07-02 4:44 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DG1 (rev3)
URL : https://patchwork.freedesktop.org/series/77496/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8689_full -> Patchwork_18063_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18063_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18063_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18063_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_fbcon_fbt@fbc:
- shard-iclb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-iclb8/igt@kms_fbcon_fbt@fbc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-iclb2/igt@kms_fbcon_fbt@fbc.html
Known issues
------------
Here are the changes found in Patchwork_18063_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#69])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl10/igt@gem_exec_suspend@basic-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl5/igt@gem_exec_suspend@basic-s3.html
* igt@kms_addfb_basic@addfb25-modifier-no-flag:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#1635] / [i915#95]) +21 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-apl8/igt@kms_addfb_basic@addfb25-modifier-no-flag.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-apl4/igt@kms_addfb_basic@addfb25-modifier-no-flag.html
* igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
- shard-snb: [PASS][7] -> [SKIP][8] ([fdo#109271])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-snb1/igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-snb4/igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#93] / [i915#95]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
- shard-skl: [PASS][11] -> [FAIL][12] ([i915#54])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +9 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl6/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl8/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][15] -> [FAIL][16] ([IGT#5])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-apl7/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-apl3/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#52] / [i915#54])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl1/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +6 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-kbl2/igt@kms_flip@flip-vs-suspend@c-dp1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
- shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-tglb3/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-tglb1/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_primary_render:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-iclb2/igt@kms_psr@psr2_primary_render.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-iclb8/igt@kms_psr@psr2_primary_render.html
* igt@perf_pmu@module-unload:
- shard-iclb: [PASS][31] -> [DMESG-WARN][32] ([i915#1982])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-iclb1/igt@perf_pmu@module-unload.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-iclb3/igt@perf_pmu@module-unload.html
#### Possible fixes ####
* igt@gem_ctx_isolation@dirty-create@vecs0:
- shard-iclb: [DMESG-WARN][33] ([i915#1226]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-iclb2/igt@gem_ctx_isolation@dirty-create@vecs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-iclb8/igt@gem_ctx_isolation@dirty-create@vecs0.html
* igt@gem_exec_reloc@basic-wc-read:
- shard-apl: [DMESG-WARN][35] ([i915#1635] / [i915#95]) -> [PASS][36] +16 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-apl6/igt@gem_exec_reloc@basic-wc-read.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-apl2/igt@gem_exec_reloc@basic-wc-read.html
* igt@gem_exec_schedule@smoketest-all:
- shard-glk: [DMESG-WARN][37] ([i915#118] / [i915#95]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-glk9/igt@gem_exec_schedule@smoketest-all.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-glk3/igt@gem_exec_schedule@smoketest-all.html
* igt@gem_exec_whisper@basic-sync-all:
- shard-hsw: [INCOMPLETE][39] -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-hsw7/igt@gem_exec_whisper@basic-sync-all.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-hsw1/igt@gem_exec_whisper@basic-sync-all.html
* igt@i915_pm_rpm@gem-pread:
- shard-skl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +5 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl3/igt@i915_pm_rpm@gem-pread.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl1/igt@i915_pm_rpm@gem-pread.html
* igt@kms_color@pipe-a-gamma:
- shard-skl: [FAIL][43] ([i915#71]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl5/igt@kms_color@pipe-a-gamma.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl8/igt@kms_color@pipe-a-gamma.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [FAIL][45] ([i915#79]) -> [PASS][46] +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@a-edp1:
- shard-skl: [FAIL][47] ([i915#1928]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
- shard-kbl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-tglb: [DMESG-WARN][51] ([i915#402]) -> [PASS][52] +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-glk: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-glk5/igt@kms_frontbuffer_tracking@fbc-stridechange.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-glk6/igt@kms_frontbuffer_tracking@fbc-stridechange.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-tglb: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][57] ([i915#1188]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl10/igt@kms_hdr@bpc-switch.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl5/igt@kms_hdr@bpc-switch.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][61] ([fdo#108145] / [i915#265]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-iclb7/igt@kms_psr@psr2_no_drrs.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_vblank@pipe-b-wait-forked:
- shard-snb: [SKIP][65] ([fdo#109271]) -> [PASS][66] +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-snb6/igt@kms_vblank@pipe-b-wait-forked.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-snb6/igt@kms_vblank@pipe-b-wait-forked.html
* igt@kms_vblank@pipe-c-wait-busy-hang:
- shard-apl: [DMESG-WARN][67] ([i915#1982]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-apl8/igt@kms_vblank@pipe-c-wait-busy-hang.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-apl4/igt@kms_vblank@pipe-c-wait-busy-hang.html
#### Warnings ####
* igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding:
- shard-kbl: [DMESG-FAIL][69] ([i915#54] / [i915#95]) -> [DMESG-WARN][70] ([i915#93] / [i915#95])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-64x21-random:
- shard-apl: [SKIP][71] ([fdo#109271] / [i915#1635]) -> [SKIP][72] ([fdo#109271]) +6 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-apl4/igt@kms_cursor_crc@pipe-d-cursor-64x21-random.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-apl8/igt@kms_cursor_crc@pipe-d-cursor-64x21-random.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [DMESG-WARN][73] ([i915#1982]) -> [DMESG-FAIL][74] ([i915#1982] / [i915#79])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-apl: [SKIP][75] ([fdo#109271]) -> [SKIP][76] ([fdo#109271] / [i915#1635]) +5 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-apl8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-apl4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [DMESG-WARN][77] ([i915#1982]) -> [FAIL][78] ([fdo#108145] / [i915#265])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-skl: [FAIL][79] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][80] ([fdo#108145] / [i915#1982])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@runner@aborted:
- shard-apl: ([FAIL][81], [FAIL][82], [FAIL][83], [FAIL][84]) ([i915#1610] / [i915#1635]) -> [FAIL][85] ([i915#1635])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-apl3/igt@runner@aborted.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-apl1/igt@runner@aborted.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-apl2/igt@runner@aborted.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8689/shard-apl2/igt@runner@aborted.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/shard-apl8/igt@runner@aborted.html
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#71]: https://gitlab.freedesktop.org/drm/intel/issues/71
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8689 -> Patchwork_18063
CI-20190529: 20190529
CI_DRM_8689: 5be0c5eb5635e500c571bea544c850d54d7d4d47 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5719: 54731f017df8660f29cc8f5db0b570239729e808 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18063: 9f3c06617494d353e430dd4cc5974579417955b9 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18063/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev4)
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (31 preceding siblings ...)
2020-07-02 4:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-07-02 7:56 ` Patchwork
2020-07-02 7:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
35 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2020-07-02 7:56 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DG1 (rev4)
URL : https://patchwork.freedesktop.org/series/77496/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dbe37e6fd3b8 drm/i915: Add has_master_unit_irq flag
a57df38e220b drm/i915/dg1: add initial DG-1 definitions
-:41: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#41: FILE: drivers/gpu/drm/i915/i915_drv.h:1565:
+#define IS_DG1_REVID(p, since, until) \
+ (IS_DG1(p) && IS_REVID(p, since, until))
total: 0 errors, 0 warnings, 1 checks, 53 lines checked
09d7a3bcfa1c drm/i915/dg1: Add DG1 PCI IDs
7645aba86977 drm/i915/dg1: add support for the master unit interrupt
a4e7d1e63681 drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
c3c8cdac1377 drm/i915/dg1: Add fake PCH
2fb5c0ccb1b8 drm/i915/dg1: Initialize RAWCLK properly
b570a1e5a878 drm/i915/dg1: Define MOCS table for DG1
b0d4b22e21ca drm/i915/dg1: Add DG1 power wells
c37b1fbd6e4c drm/i915/dg1: Increase mmio size to 4MB
3a7db869077a drm/i915/dg1: Wait for pcode/uncore handshake at startup
29c1c8aa23b1 drm/i915/dg1: Add DPLL macros for DG1
b35df30e60c1 drm/i915/dg1: Add and setup DPLLs for DG1
51e0bbafd49f drm/i915/dg1: Enable DPLL for DG1
453927842498 drm/i915/dg1: add hpd interrupt handling
87e49290c0ab drm/i915/dg1: invert HPD pins
5d8f741133ed drm/i915/dg1: gmbus pin mapping
ef8b7dbd1018 drm/i915/dg1: Enable first 2 ports for DG1
4815d78bced9 drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
2cefb9635321 drm/i915/dg1: Update comp master/slave relationships for PHYs
29631f3b16ff drm/i915/dg1: Update voltage swing tables for DP
4d0feb983cfb drm/i915/dg1: provide port/phy mapping for vbt
75b64397b636 drm/i915/dg1: map/unmap pll clocks
-:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects?
#244: FILE: drivers/gpu/drm/i915/i915_reg.h:10305:
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \
+ ((((val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2)))
total: 0 errors, 0 warnings, 1 checks, 204 lines checked
667ccc4421b2 drm/i915/dg1: enable PORT C/D aka D/E
3405f35bf028 drm/i915/dg1: Load DMC
2b7a3b38daa6 drm/i915/rkl: Add initial workarounds
838479249b59 drm/i915/dg1: Add initial DG1 workarounds
18c2a8bf107b drm/i915/dg1: DG1 does not support DC6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce DG1 (rev4)
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (32 preceding siblings ...)
2020-07-02 7:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 (rev4) Patchwork
@ 2020-07-02 7:57 ` Patchwork
2020-07-02 8:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-02 11:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
35 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2020-07-02 7:57 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DG1 (rev4)
URL : https://patchwork.freedesktop.org/series/77496/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1223:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1226:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1229:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1232:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2267:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2268:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion
+drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion
+drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce DG1 (rev4)
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (33 preceding siblings ...)
2020-07-02 7:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-07-02 8:20 ` Patchwork
2020-07-02 11:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
35 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2020-07-02 8:20 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DG1 (rev4)
URL : https://patchwork.freedesktop.org/series/77496/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8691 -> Patchwork_18064
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/index.html
Known issues
------------
Here are the changes found in Patchwork_18064 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [FAIL][7] ([i915#1888]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Warnings ####
* igt@debugfs_test@read_all_entries:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/fi-kbl-x1275/igt@debugfs_test@read_all_entries.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/fi-kbl-x1275/igt@debugfs_test@read_all_entries.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (42 -> 37)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper
Build changes
-------------
* Linux: CI_DRM_8691 -> Patchwork_18064
CI-20190529: 20190529
CI_DRM_8691: 65f4b41f875158ce36b3571700c0f39e8321332a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5719: 54731f017df8660f29cc8f5db0b570239729e808 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18064: 18c2a8bf107b64041778f658bacc2631ef8a9268 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
18c2a8bf107b drm/i915/dg1: DG1 does not support DC6
838479249b59 drm/i915/dg1: Add initial DG1 workarounds
2b7a3b38daa6 drm/i915/rkl: Add initial workarounds
3405f35bf028 drm/i915/dg1: Load DMC
667ccc4421b2 drm/i915/dg1: enable PORT C/D aka D/E
75b64397b636 drm/i915/dg1: map/unmap pll clocks
4d0feb983cfb drm/i915/dg1: provide port/phy mapping for vbt
29631f3b16ff drm/i915/dg1: Update voltage swing tables for DP
2cefb9635321 drm/i915/dg1: Update comp master/slave relationships for PHYs
4815d78bced9 drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
ef8b7dbd1018 drm/i915/dg1: Enable first 2 ports for DG1
5d8f741133ed drm/i915/dg1: gmbus pin mapping
87e49290c0ab drm/i915/dg1: invert HPD pins
453927842498 drm/i915/dg1: add hpd interrupt handling
51e0bbafd49f drm/i915/dg1: Enable DPLL for DG1
b35df30e60c1 drm/i915/dg1: Add and setup DPLLs for DG1
29c1c8aa23b1 drm/i915/dg1: Add DPLL macros for DG1
3a7db869077a drm/i915/dg1: Wait for pcode/uncore handshake at startup
c37b1fbd6e4c drm/i915/dg1: Increase mmio size to 4MB
b0d4b22e21ca drm/i915/dg1: Add DG1 power wells
b570a1e5a878 drm/i915/dg1: Define MOCS table for DG1
2fb5c0ccb1b8 drm/i915/dg1: Initialize RAWCLK properly
c3c8cdac1377 drm/i915/dg1: Add fake PCH
a4e7d1e63681 drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
7645aba86977 drm/i915/dg1: add support for the master unit interrupt
09d7a3bcfa1c drm/i915/dg1: Add DG1 PCI IDs
a57df38e220b drm/i915/dg1: add initial DG-1 definitions
dbe37e6fd3b8 drm/i915: Add has_master_unit_irq flag
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce DG1 (rev4)
2020-07-01 23:53 [Intel-gfx] [PATCH v3 00/28] Introduce DG1 Lucas De Marchi
` (34 preceding siblings ...)
2020-07-02 8:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-07-02 11:03 ` Patchwork
35 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2020-07-02 11:03 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Introduce DG1 (rev4)
URL : https://patchwork.freedesktop.org/series/77496/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8691_full -> Patchwork_18064_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18064_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18064_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18064_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ctx_persistence@engines-mixed@vecs0:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-skl7/igt@gem_ctx_persistence@engines-mixed@vecs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-skl3/igt@gem_ctx_persistence@engines-mixed@vecs0.html
* igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge:
- shard-hsw: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-hsw8/igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-hsw8/igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge.html
Known issues
------------
Here are the changes found in Patchwork_18064_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd2:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#1528])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-tglb1/igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd2.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-tglb1/igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd2.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy:
- shard-snb: [PASS][7] -> [TIMEOUT][8] ([i915#1958] / [i915#2119])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-snb5/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-snb2/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_addfb_basic@addfb25-modifier-no-flag:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1635] / [i915#95]) +18 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-apl8/igt@kms_addfb_basic@addfb25-modifier-no-flag.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-apl4/igt@kms_addfb_basic@addfb25-modifier-no-flag.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#93] / [i915#95]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-kbl2/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-kbl6/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180] / [i915#93] / [i915#95])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +12 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-skl10/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-skl2/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
* igt@kms_flip@2x-modeset-vs-vblank-race@ab-vga1-hdmi-a1:
- shard-hsw: [PASS][19] -> [DMESG-WARN][20] ([i915#1982])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-hsw7/igt@kms_flip@2x-modeset-vs-vblank-race@ab-vga1-hdmi-a1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-hsw6/igt@kms_flip@2x-modeset-vs-vblank-race@ab-vga1-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-vga1:
- shard-hsw: [PASS][21] -> [FAIL][22] ([i915#79])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-hsw1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-vga1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-hsw7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-vga1.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#1928])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-skl8/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-skl5/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-glk: [PASS][25] -> [DMESG-WARN][26] ([i915#1982])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-glk4/igt@kms_frontbuffer_tracking@fbc-stridechange.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-glk6/igt@kms_frontbuffer_tracking@fbc-stridechange.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
- shard-tglb: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-tglb7/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-tglb2/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html
* igt@kms_sysfs_edid_timing:
- shard-iclb: [PASS][29] -> [FAIL][30] ([IGT#2])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-iclb5/igt@kms_sysfs_edid_timing.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-iclb2/igt@kms_sysfs_edid_timing.html
* igt@perf_pmu@busy-double-start@rcs0:
- shard-snb: [PASS][31] -> [FAIL][32] ([i915#1958]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-snb5/igt@perf_pmu@busy-double-start@rcs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-snb2/igt@perf_pmu@busy-double-start@rcs0.html
* igt@perf_pmu@busy-double-start@vcs0:
- shard-snb: [PASS][33] -> [INCOMPLETE][34] ([i915#2119] / [i915#82])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-snb5/igt@perf_pmu@busy-double-start@vcs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-snb2/igt@perf_pmu@busy-double-start@vcs0.html
#### Possible fixes ####
* igt@gem_ctx_persistence@engines-mixed-process@vecs0:
- shard-kbl: [FAIL][35] ([i915#1528]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-kbl7/igt@gem_ctx_persistence@engines-mixed-process@vecs0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-kbl3/igt@gem_ctx_persistence@engines-mixed-process@vecs0.html
* igt@gem_ctx_persistence@hostile:
- shard-apl: [DMESG-WARN][37] ([i915#1635] / [i915#95]) -> [PASS][38] +19 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-apl7/igt@gem_ctx_persistence@hostile.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-apl8/igt@gem_ctx_persistence@hostile.html
* igt@gem_eio@kms:
- shard-kbl: [DMESG-WARN][39] ([i915#93] / [i915#95]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-kbl2/igt@gem_eio@kms.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-kbl1/igt@gem_eio@kms.html
* igt@i915_selftest@mock@requests:
- shard-skl: [INCOMPLETE][41] ([i915#198] / [i915#2110]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-skl4/igt@i915_selftest@mock@requests.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-skl8/igt@i915_selftest@mock@requests.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-0:
- shard-glk: [DMESG-FAIL][43] ([i915#118] / [i915#95]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-glk3/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-apl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-apl6/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-apl7/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_color@pipe-a-gamma:
- shard-skl: [FAIL][47] ([i915#71]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-skl6/igt@kms_color@pipe-a-gamma.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-skl6/igt@kms_color@pipe-a-gamma.html
* igt@kms_color@pipe-b-ctm-0-75:
- shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-skl8/igt@kms_color@pipe-b-ctm-0-75.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-skl10/igt@kms_color@pipe-b-ctm-0-75.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
- shard-glk: [DMESG-FAIL][51] ([i915#1982] / [i915#54]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-glk4/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-glk2/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-hsw: [FAIL][53] ([i915#57]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-hsw2/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@pipe-a-single-bo:
- shard-glk: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-glk4/igt@kms_cursor_legacy@pipe-a-single-bo.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-glk2/igt@kms_cursor_legacy@pipe-a-single-bo.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled:
- shard-glk: [DMESG-FAIL][57] ([i915#118] / [i915#1982] / [i915#54] / [i915#95]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-glk4/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-glk2/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-iclb: [INCOMPLETE][59] ([i915#1185]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-iclb2/igt@kms_fbcon_fbt@psr-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-iclb4/igt@kms_fbcon_fbt@psr-suspend.html
- shard-skl: [INCOMPLETE][61] ([i915#69]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-skl1/igt@kms_fbcon_fbt@psr-suspend.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-skl4/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][63] ([i915#79]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render:
- shard-iclb: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-glk: [DMESG-FAIL][67] ([i915#118] / [i915#1982] / [i915#49] / [i915#95]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-glk4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-glk2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack:
- shard-tglb: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-skl: [FAIL][71] ([i915#49]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][73] ([i915#1188]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-iclb: [INCOMPLETE][75] ([i915#1185] / [i915#250]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-iclb5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][77] ([fdo#108145] / [i915#265]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][79] ([i915#180]) -> [PASS][80] +7 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@sysfs_timeslice_duration@timeout@vecs0:
- shard-glk: [INCOMPLETE][81] ([i915#58] / [k.org#198133]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-glk4/igt@sysfs_timeslice_duration@timeout@vecs0.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-glk2/igt@sysfs_timeslice_duration@timeout@vecs0.html
- shard-apl: [FAIL][83] ([i915#1732]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-apl6/igt@sysfs_timeslice_duration@timeout@vecs0.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-apl3/igt@sysfs_timeslice_duration@timeout@vecs0.html
#### Warnings ####
* igt@gem_exec_reloc@basic-concurrent16:
- shard-snb: [FAIL][85] ([i915#1930]) -> [TIMEOUT][86] ([i915#1958] / [i915#2119])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-snb5/igt@gem_exec_reloc@basic-concurrent16.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-snb2/igt@gem_exec_reloc@basic-concurrent16.html
* igt@i915_pm_dc@dc5-dpms:
- shard-snb: [SKIP][87] ([fdo#109271]) -> [INCOMPLETE][88] ([i915#82])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-snb2/igt@i915_pm_dc@dc5-dpms.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-snb4/igt@i915_pm_dc@dc5-dpms.html
* igt@kms_content_protection@lic:
- shard-kbl: [TIMEOUT][89] ([i915#1319] / [i915#2119]) -> [TIMEOUT][90] ([i915#1319] / [i915#1958] / [i915#2119])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-kbl6/igt@kms_content_protection@lic.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-kbl7/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-random:
- shard-snb: [SKIP][91] ([fdo#109271]) -> [TIMEOUT][92] ([i915#1958] / [i915#2119]) +3 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-snb5/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-snb2/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-apl: [SKIP][93] ([fdo#109271]) -> [SKIP][94] ([fdo#109271] / [i915#1635]) +11 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-apl8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-apl4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-farfromfence:
- shard-apl: [SKIP][95] ([fdo#109271] / [i915#1635]) -> [SKIP][96] ([fdo#109271]) +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-apl7/igt@kms_frontbuffer_tracking@fbcpsr-farfromfence.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-apl8/igt@kms_frontbuffer_tracking@fbcpsr-farfromfence.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-skl: [FAIL][97] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][98] ([fdo#108145] / [i915#1982])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@runner@aborted:
- shard-hsw: ([FAIL][99], [FAIL][100]) ([i915#2110]) -> [FAIL][101] ([i915#1436] / [i915#2110])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-hsw7/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-hsw7/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-hsw7/igt@runner@aborted.html
- shard-iclb: ([FAIL][102], [FAIL][103], [FAIL][104]) ([i915#2110]) -> ([FAIL][105], [FAIL][106]) ([i915#1927] / [i915#2110])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-iclb1/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-iclb7/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8691/shard-iclb4/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-iclb1/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/shard-iclb7/igt@runner@aborted.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1732]: https://gitlab.freedesktop.org/drm/intel/issues/1732
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927
[i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928
[i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110
[i915#2119]: https://gitlab.freedesktop.org/drm/intel/issues/2119
[i915#250]: https://gitlab.freedesktop.org/drm/intel/issues/250
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#71]: https://gitlab.freedesktop.org/drm/intel/issues/71
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8691 -> Patchwork_18064
CI-20190529: 20190529
CI_DRM_8691: 65f4b41f875158ce36b3571700c0f39e8321332a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5719: 54731f017df8660f29cc8f5db0b570239729e808 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18064: 18c2a8bf107b64041778f658bacc2631ef8a9268 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18064/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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