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From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [RFC 58/60] drm/i915/dg1: Reserve first 1MB of local memory
Date: Fri, 10 Jul 2020 12:57:55 +0100	[thread overview]
Message-ID: <20200710115757.290984-59-matthew.auld@intel.com> (raw)
In-Reply-To: <20200710115757.290984-1-matthew.auld@intel.com>

From: Imre Deak <imre.deak@intel.com>

On DG1 A0 stepping the first 1MB of local memory must be reserved. One
reason for this is that the 0xA0000-0xB0000 range is not accessible by
the display, probably since this region is redirected to another memory
location for legacy VGA compatibility.

BSpec: 60029
Testcase: igt/kms_big_fb/linear-64bpp-rotate-0
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_region_lmem.c | 52 ++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c b/drivers/gpu/drm/i915/intel_region_lmem.c
index 46a2aa468054..b9e60d19d07c 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -41,6 +41,48 @@ const struct intel_memory_region_ops intel_region_lmem_ops = {
 	.create_object = __i915_gem_lmem_object_create,
 };
 
+static void get_legacy_lowmem_region(struct intel_uncore *uncore,
+				     u64 *start, u32 *size)
+{
+	*start = 0;
+	*size = 0;
+
+	if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_A0))
+		return;
+
+	*size = SZ_1M;
+
+	DRM_DEBUG_DRIVER("LMEM: reserved legacy low-memory [0x%llx-0x%llx]\n",
+			 *start, *start + *size);
+}
+
+static int reserve_lowmem_region(struct intel_uncore *uncore,
+				 struct intel_memory_region *mem)
+{
+	u64 reserve_start;
+	u64 reserve_end;
+	u64 region_start;
+	u32 region_size;
+	int ret;
+
+	get_legacy_lowmem_region(uncore, &region_start, &region_size);
+	reserve_start = region_start;
+	reserve_end = region_start + region_size;
+
+	if (!reserve_end)
+		return 0;
+
+	DRM_INFO("LMEM: reserving low-memory region [0x%llx-0x%llx]\n",
+		 reserve_start, reserve_end);
+	ret = i915_buddy_alloc_range(&mem->mm, &mem->reserved,
+				     reserve_start,
+				     reserve_end - reserve_start);
+	if (ret)
+		DRM_ERROR("LMEM: reserving low memory region failed\n");
+
+	return ret;
+}
+
 static struct intel_memory_region *
 setup_lmem(struct drm_i915_private *dev_priv)
 {
@@ -64,6 +106,16 @@ setup_lmem(struct drm_i915_private *dev_priv)
 					 I915_GTT_PAGE_SIZE_4K,
 					 io_start,
 					 &intel_region_lmem_ops);
+	if (!IS_ERR(mem)) {
+		int err;
+
+		err = reserve_lowmem_region(uncore, mem);
+		if (err) {
+			intel_memory_region_put(mem);
+			return ERR_PTR(err);
+		}
+	}
+
 	if (!IS_ERR(mem)) {
 		DRM_INFO("Intel graphics LMEM: %pR\n", &mem->region);
 		DRM_INFO("Intel graphics LMEM IO start: %llx\n",
-- 
2.26.2

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  parent reply	other threads:[~2020-07-10 12:02 UTC|newest]

Thread overview: 87+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
2020-07-10 11:56 ` [Intel-gfx] [RFC 01/60] drm/i915: Add has_master_unit_irq flag Matthew Auld
2020-07-10 11:56 ` [Intel-gfx] [RFC 02/60] drm/i915/dg1: add initial DG-1 definitions Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 03/60] drm/i915/dg1: Add DG1 PCI IDs Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 04/60] drm/i915/dg1: add support for the master unit interrupt Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 05/60] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 06/60] drm/i915/dg1: Add fake PCH Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 07/60] drm/i915/dg1: Initialize RAWCLK properly Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 08/60] drm/i915/dg1: Define MOCS table for DG1 Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 09/60] drm/i915/dg1: Add DG1 power wells Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 10/60] drm/i915/dg1: Increase mmio size to 4MB Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 11/60] drm/i915/dg1: Wait for pcode/uncore handshake at startup Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 12/60] drm/i915/dg1: Add DPLL macros for DG1 Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 13/60] drm/i915/dg1: Add and setup DPLLs " Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 14/60] drm/i915/dg1: Enable DPLL " Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 15/60] drm/i915/dg1: add hpd interrupt handling Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 16/60] drm/i915/dg1: invert HPD pins Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 17/60] drm/i915/dg1: gmbus pin mapping Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 18/60] drm/i915/dg1: Enable first 2 ports for DG1 Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 19/60] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 20/60] drm/i915/dg1: Update comp master/slave relationships for PHYs Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 21/60] drm/i915/dg1: Update voltage swing tables for DP Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 22/60] drm/i915/dg1: provide port/phy mapping for vbt Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 23/60] drm/i915/dg1: map/unmap pll clocks Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 24/60] drm/i915/dg1: enable PORT C/D aka D/E Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 25/60] drm/i915/dg1: Load DMC Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 26/60] drm/i915/rkl: Add initial workarounds Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 27/60] drm/i915/dg1: Add initial DG1 workarounds Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 28/60] drm/i915/dg1: DG1 does not support DC6 Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 29/60] drm/i915/lmem: Limit block size to 4G Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 30/60] drm/i915/lmem: Do not check r->sgt.pfn for NULL Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 31/60] drm/i915/dgfx: define llc and snooping behaviour Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 32/60] drm/i915/lmem: support pread Matthew Auld
2020-07-10 12:39   ` Tvrtko Ursulin
2020-07-10 13:04     ` Chris Wilson
2020-07-10 11:57 ` [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite Matthew Auld
2020-07-13  5:09   ` Dave Airlie
2020-07-14 14:35     ` Matthew Auld
2020-07-16  0:43       ` Dave Airlie
2020-07-16 10:11         ` Matthew Auld
2020-07-19 21:52           ` Dave Airlie
2020-08-07  9:32             ` Joonas Lahtinen
2020-08-07  9:46     ` Joonas Lahtinen
2020-08-09 21:06       ` Dave Airlie
2020-07-10 11:57 ` [Intel-gfx] [RFC 34/60] drm/i915: introduce kernel blitter_context Matthew Auld
2020-08-03 19:59   ` Lucas De Marchi
2020-08-03 20:17     ` Lucas De Marchi
2020-07-10 11:57 ` [Intel-gfx] [RFC 35/60] drm/i915/query: Expose memory regions through the query uAPI Matthew Auld
2020-07-10 16:20   ` Tvrtko Ursulin
2020-07-10 11:57 ` [Intel-gfx] [RFC 36/60] drm/i915/uapi: introduce drm_i915_gem_create_ext Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 37/60] drm/i915/lmem: allocate cmd ring in lmem Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 38/60] drm/i915/dg1: Introduce dmabuf mmap to LMEM Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 39/60] drm/i915: setup the LMEM region Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 40/60] drm/i915: drop fake LMEM Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 41/60] drm/i915: Distinction of memory regions Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 42/60] drm/i915: PPGTT support Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 43/60] drm/i915: support GGTT LMEM entries Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 44/60] drm/i915: allocate context from LMEM Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 45/60] drm/i915: move engine scratch to LMEM Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 46/60] drm/i915: Provide a way to disable PCIe relaxed write ordering Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 47/60] drm/i915: setup GPU device lmem region Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 48/60] drm/i915: Fix object page offset within a region Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 49/60] drm/i915: add i915_gem_object_is_devmem() function Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 50/60] drm/i915: finish memory region support for stolen objects Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 51/60] drm/i915/lmem: support optional CPU clearing for special internal use Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 52/60] drm/i915/guc: put all guc objects in lmem when available Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory Matthew Auld
2020-07-13  4:48   ` Dave Airlie
2020-07-14 15:01     ` Matthew Auld
2020-07-14 16:57       ` Tang, CQ
2020-07-14 19:26         ` Dave Airlie
2020-08-07  9:38           ` Joonas Lahtinen
2020-08-07 16:24             ` Tang, CQ
2020-07-14 17:39       ` Ville Syrjälä
2020-07-10 11:57 ` [Intel-gfx] [RFC 54/60] drm/i915/lmem: Bypass aperture when lmem is available Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 55/60] drm/i915/lmem: reset the lmem buffer created by fbdev Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 56/60] drm/i915/dsb: Enable lmem for dsb Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 57/60] drm/i915: Reintroduce mem->reserved Matthew Auld
2020-07-10 11:57 ` Matthew Auld [this message]
2020-07-10 11:57 ` [Intel-gfx] [RFC 59/60] drm/i915: defer pd lmem block put to worker Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 60/60] drm/i915/lmem: allocate HWSP in lmem Matthew Auld
2020-07-10 12:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DG1 LMEM enabling Patchwork
2020-07-10 12:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-10 13:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-10 14:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-08-11  3:23 ` [Intel-gfx] [RFC 00/60] " Dave Airlie
2020-08-11 10:48   ` Matthew Auld

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