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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/ddi: Don't rewrite DDI_BUF_CTL reg during DP link training
Date: Tue, 14 Jul 2020 19:08:33 +0300	[thread overview]
Message-ID: <20200714160833.GL6112@intel.com> (raw)
In-Reply-To: <20200714153141.10280-2-imre.deak@intel.com>

On Tue, Jul 14, 2020 at 06:31:41PM +0300, Imre Deak wrote:
> The driver enables the DDI function in the DDI_BUF_CTL register before
> starting the link training and disables it when disabling the output. It
> also gets disabled/re-enabled during link re-trainining.
> 
> Except of the above the value we program to the register (intel_dp->DP)
> doesn't change, so no need to reprogram the register when changing the
> link training patterns.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

The only concern I had was the buf trans stuff for hsw/bdw/skl,
but looks like hsw_set_signal_levels() does everything we need.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c467f18d5e1b..424d59671561 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4060,7 +4060,6 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
> -	enum port port = dp_to_dig_port(intel_dp)->base.port;
>  	u32 temp;
>  
>  	temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> @@ -4085,9 +4084,6 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
>  	}
>  
>  	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
> -
> -	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> -	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
>  }
>  
>  static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)
> -- 
> 2.23.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-07-14 16:08 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-14 15:31 [Intel-gfx] [PATCH 1/2] drm/i915/ddi: Don't frob the DP link scramble disabling flag Imre Deak
2020-07-14 15:31 ` [Intel-gfx] [PATCH 2/2] drm/i915/ddi: Don't rewrite DDI_BUF_CTL reg during DP link training Imre Deak
2020-07-14 16:08   ` Ville Syrjälä [this message]
2020-07-14 16:20     ` Imre Deak
2020-07-14 16:05 ` [Intel-gfx] [PATCH 1/2] drm/i915/ddi: Don't frob the DP link scramble disabling flag Ville Syrjälä
2020-07-14 16:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2020-07-14 18:17 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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