Re: [Intel-gfx] [PATCH v2] drm/i915/gt: Implement WA_1406941453

From: Matt Roper <matthew.d.roper@intel.com>
To: clinton.a.taylor@intel.com
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/gt: Implement WA_1406941453
Date: Wed, 12 Aug 2020 14:53:49 -0700	[thread overview]
Message-ID: <20200812215349.GD2903088@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20200805232920.15085-1-clinton.a.taylor@intel.com>

On Wed, Aug 05, 2020 at 04:29:20PM -0700, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
> 
> Enable HW Default flip for small PL.
> 
> bspec: 52890
> bspec: 53508
> bspec: 53273
> 
> v2: rebase to drm-tip
> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
>  drivers/gpu/drm/i915/i915_reg.h             | 1 +
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index cef1c122696f..cb02813c5e92 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -639,6 +639,9 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  	       FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
>  	       FF_MODE2_GS_TIMER_224  | FF_MODE2_TDS_TIMER_128,
>  	       0);
> +
> +	/* Wa_1406941453:gen12 */
> +	WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, ENABLE_SMALLPL);

Is this register part of the engine context on gen12?  I see it in the
context for ICL (bspec 18907), but not for TGL (46255).  So I think this
should either be a GT or engine workaround, not a context workaround,
right?

>  }
>  
>  static void
> @@ -1522,6 +1525,9 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>  		whitelist_reg_ext(w, PS_INVOCATION_COUNT,
>  				  RING_FORCE_TO_NONPRIV_ACCESS_RD |
>  				  RING_FORCE_TO_NONPRIV_RANGE_4);
> +
> +		/* Wa_1406941453:gen12 */
> +		whitelist_reg(w, GEN10_SAMPLER_MODE);

Do we need to whitelist this?  If we're applying the workaround in the
kernel then the UMD shouldn't need to worry about it if they don't
otherwise have access or need to change the register value.

Matt

>  		break;
>  
>  	case VIDEO_DECODE_CLASS:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2b403df03404..494b2e1e358e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9314,6 +9314,7 @@ enum {
>  #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
>  
>  #define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
> +#define   ENABLE_SMALLPL			REG_BIT(15)
>  #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
>  
>  /* IVYBRIDGE DPF */
> -- 
> 2.27.0
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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