Re: [Intel-gfx] [PATCH v9 8/8] drm/i915: Enable async flips in i915

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Wed, Sep 16, 2020 at 08:38:24PM +0530, Karthik B S wrote:
> Enable asynchronous flips in i915 for gen9+ platforms.
> 
> v2: -Async flip enablement should be a stand alone patch (Paulo)
> 
> v3: -Move the patch to the end of the series (Paulo)
> 
> v4: -Rebased.
> 
> v5: -Rebased.
> 
> v6: -Rebased.
> 
> v7: -Rebased.
> 
> v8: -Rebased.
> 
> v9: -Rebased.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6f6edc581e14..e31abf5f1a9d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -18021,6 +18021,9 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
>  
>  	mode_config->funcs = &intel_mode_funcs;
>  
> +	if (INTEL_GEN(i915) >= 9)
> +		mode_config->async_page_flip = true;
> +

Should have all we need for those platforms I think.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

The followup to enable it for ilk+ would require a slight change to
bump X-tiled surface alignment to 256KiB. Apart from the actual regiser
smashing part that should be all we need really.

Oh, and the double buffer bit w/a will also be needed on bdw.
I've now tested snb/ivb/hsw/bdw and only bdw needs it. I guess
that's not entirely unsurpising since bdw did introduce one other
fail for the flip done interrupt (the interupt fires immediately 
when the plane was disabled, so can't use flip done to determine
when the plane has actually become visible). Fortunately that
other fail should have no impact on using it for async flip
completion.

>  	/*
>  	 * Maximum framebuffer dimensions, chosen to match
>  	 * the maximum render engine surface size on gen4+.
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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