From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 5/5] drm/i915/tgl: Add workaround for incorrect BIOS combo PHY DPLL programming
Date: Tue, 29 Sep 2020 03:29:29 +0300 [thread overview]
Message-ID: <20200929002929.783620-6-imre.deak@intel.com> (raw)
In-Reply-To: <20200929002929.783620-1-imre.deak@intel.com>
The TGL A stepping and some B stepping (display C stepping) BIOSes
program the combo PHY DPLL fractional divider value incorrectly, not
applying the Display #22010492432 workaround.
Add a workaround for such BIOS versions, so that the driver selects the
correct WRPLL parameter entry correctly (selecting the same entry from
the table whether or not the fractional divider was adjusted or not by
BIOS according to #22010492432).
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e7b058340a1a..7968ceb23ab6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3026,7 +3026,15 @@ static bool icl_dp_combo_pll_clock_match(struct drm_i915_private *i915, int cloc
if (clock == pll_freq)
return true;
- return false;
+ if (!tgl_combo_pll_div_frac_wa_needed(i915) ||
+ !IS_TGL_DISP_REVID(i915, TGL_REVID_A0, TGL_REVID_C0))
+ return false;
+
+ pll_freq = skl_wrpll_calc_freq(ref_clock,
+ p->wrpll.dco_integer, p->wrpll.dco_fraction * 2,
+ pdiv, qdiv, kdiv);
+
+ return clock == pll_freq;
}
static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
--
2.25.1
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next prev parent reply other threads:[~2020-09-29 0:29 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-29 0:29 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
2020-09-29 0:29 ` [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming Imre Deak
2020-10-01 16:41 ` Ville Syrjälä
2020-10-01 16:53 ` Imre Deak
2020-09-29 0:29 ` [Intel-gfx] [PATCH 2/5] drm/i915: Factor out skl_wrpll_calc_freq() Imre Deak
2020-09-29 0:29 ` [Intel-gfx] [PATCH 3/5] drm/i915/icl: Cross check the combo PLL WRPLL parameters wrt. hard-coded PLL freqs Imre Deak
2020-10-01 16:44 ` Ville Syrjälä
2020-10-01 17:00 ` Ville Syrjälä
2020-10-01 17:31 ` Imre Deak
2020-09-29 0:29 ` [Intel-gfx] [PATCH 4/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
2020-10-01 16:45 ` Ville Syrjälä
2020-09-29 0:29 ` Imre Deak [this message]
2020-09-29 1:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
2020-09-29 2:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
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