From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
Date: Tue, 29 Sep 2020 03:29:24 +0300 [thread overview]
Message-ID: <20200929002929.783620-1-imre.deak@intel.com> (raw)
This patchset replaces [1], adding also a workaround for TGL BIOSes that
don't apply Display WA #22010492432. The first patch fixes an incorrect
BIOS PDIV programming I noticed while testing this patchset on an ASUS/SKL
system.
[1] https://patchwork.freedesktop.org/series/79486/
Imre Deak (5):
drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
drm/i915: Factor out skl_wrpll_calc_freq()
drm/i915/icl: Cross check the combo PLL WRPLL parameters wrt.
hard-coded PLL freqs
drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref
clock
drm/i915/tgl: Add workaround for incorrect BIOS combo PHY DPLL
programming
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 232 ++++++++++++------
drivers/gpu/drm/i915/i915_reg.h | 4 +
2 files changed, 161 insertions(+), 75 deletions(-)
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next reply other threads:[~2020-09-29 0:29 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-29 0:29 Imre Deak [this message]
2020-09-29 0:29 ` [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming Imre Deak
2020-10-01 16:41 ` Ville Syrjälä
2020-10-01 16:53 ` Imre Deak
2020-09-29 0:29 ` [Intel-gfx] [PATCH 2/5] drm/i915: Factor out skl_wrpll_calc_freq() Imre Deak
2020-09-29 0:29 ` [Intel-gfx] [PATCH 3/5] drm/i915/icl: Cross check the combo PLL WRPLL parameters wrt. hard-coded PLL freqs Imre Deak
2020-10-01 16:44 ` Ville Syrjälä
2020-10-01 17:00 ` Ville Syrjälä
2020-10-01 17:31 ` Imre Deak
2020-09-29 0:29 ` [Intel-gfx] [PATCH 4/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
2020-10-01 16:45 ` Ville Syrjälä
2020-09-29 0:29 ` [Intel-gfx] [PATCH 5/5] drm/i915/tgl: Add workaround for incorrect BIOS combo PHY DPLL programming Imre Deak
2020-09-29 1:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Patchwork
2020-09-29 2:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2020-10-03 0:18 [Intel-gfx] [PATCH 0/5] " Imre Deak
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200929002929.783620-1-imre.deak@intel.com \
--to=imre.deak@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox