From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
Date: Sat, 3 Oct 2020 03:18:41 +0300 [thread overview]
Message-ID: <20201003001846.1271151-1-imre.deak@intel.com> (raw)
This patchset replaces [1]. That version's solution to work around
broken TGL A BIOSes turned out to be papering over something. The real
root cause was the lack of a full encoder recompute/modeset during the
initial commit and leaking the incorrect link rate into the PLL
frequency calculation code. So instead of making the PLL code aware of
incorrect link rates, this patchset forces a full modeset which will
recompute the correct link rate.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
[1] https://patchwork.freedesktop.org/series/82173/
Imre Deak (5):
drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
drm/i915: Move the initial fastset commit check to encoder hooks
drm/i915: Check for unsupported DP link rates during initial commit
drm/i915: Add an encoder hook to sanitize its state during init/resume
drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref
clock
drivers/gpu/drm/i915/display/icl_dsi.c | 14 ++++
drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++++
drivers/gpu/drm/i915/display/intel_display.c | 33 +++++-----
.../drm/i915/display/intel_display_types.h | 15 +++++
drivers/gpu/drm/i915/display/intel_dp.c | 65 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 5 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 20 ++++++
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 55 +++++++++++-----
drivers/gpu/drm/i915/i915_reg.h | 1 +
9 files changed, 194 insertions(+), 32 deletions(-)
--
2.25.1
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next reply other threads:[~2020-10-03 0:18 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-03 0:18 Imre Deak [this message]
2020-10-03 0:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming Imre Deak
2020-10-05 20:08 ` Ville Syrjälä
2020-10-05 20:26 ` Imre Deak
2020-10-05 23:37 ` Ville Syrjälä
2020-10-06 1:24 ` Imre Deak
2020-10-06 1:35 ` [Intel-gfx] [PATCH v3 " Imre Deak
2020-10-06 8:59 ` Ville Syrjälä
2020-10-03 0:18 ` [Intel-gfx] [PATCH 2/5] drm/i915: Move the initial fastset commit check to encoder hooks Imre Deak
2020-10-03 1:07 ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-10-05 20:24 ` Ville Syrjälä
2020-10-05 20:34 ` Imre Deak
2020-10-05 21:53 ` [Intel-gfx] [PATCH v3 " Imre Deak
2020-10-06 9:42 ` Jani Nikula
2020-10-06 9:55 ` Imre Deak
2020-10-06 10:00 ` Jani Nikula
2020-10-06 10:05 ` Imre Deak
2020-10-03 0:18 ` [Intel-gfx] [PATCH 3/5] drm/i915: Check for unsupported DP link rates during initial commit Imre Deak
2020-10-05 20:25 ` Ville Syrjälä
2020-10-03 0:18 ` [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume Imre Deak
2020-10-05 20:30 ` Ville Syrjälä
2020-10-05 20:46 ` Imre Deak
2020-10-05 23:39 ` Ville Syrjälä
2020-10-05 20:40 ` Ville Syrjälä
2020-10-05 20:57 ` Imre Deak
2020-10-05 20:51 ` Ville Syrjälä
2020-10-05 23:00 ` Imre Deak
2020-10-05 21:53 ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-10-05 23:01 ` [Intel-gfx] [PATCH v3 " Imre Deak
2020-10-06 8:58 ` Ville Syrjälä
2020-10-03 0:18 ` [Intel-gfx] [PATCH 5/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
2020-10-03 0:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2) Patchwork
2020-10-03 0:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-03 1:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3) Patchwork
2020-10-03 1:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-03 3:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-10-03 13:48 ` Imre Deak
2020-10-04 6:12 ` Vudum, Lakshminarayana
2020-10-04 5:47 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2020-10-06 0:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) Patchwork
2020-10-06 0:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-06 1:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7) Patchwork
2020-10-06 2:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-06 2:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) Patchwork
2020-10-06 10:32 ` Imre Deak
2020-10-06 11:04 ` Imre Deak
2020-10-06 5:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2020-09-29 0:29 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
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