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From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org,
	Lakshminarayana Vudum <lakshminarayana.vudum@intel.com>,
	Tomi P Sarvela <tomi.p.sarvela@intel.com>
Subject: Re: [Intel-gfx]  ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
Date: Sat, 3 Oct 2020 16:48:54 +0300	[thread overview]
Message-ID: <20201003134854.GA1278041@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <160169736013.24066.4200219438161051461@emeril.freedesktop.org>

Hi Lakshmi, Tomi,

On Sat, Oct 03, 2020 at 03:56:00AM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
> URL   : https://patchwork.freedesktop.org/series/82173/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_9093_full -> Patchwork_18620_full
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_18620_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_18620_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in Patchwork_18620_full:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@gem_userptr_blits@unsync-unmap-cycles:
>     - shard-skl:          [PASS][1] -> [TIMEOUT][2]
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-skl6/igt@gem_userptr_blits@unsync-unmap-cycles.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-skl4/igt@gem_userptr_blits@unsync-unmap-cycles.html

This looks like
https://gitlab.freedesktop.org/drm/intel/-/issues/2424
still happening at
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9090/shard-skl5/igt@gem_userptr_blits@sync-unmap-cycles.html

Could you update the filter to include sync-unmap-cycles as well?


>   * igt@kms_flip@flip-vs-suspend@c-edp1:
>     - shard-iclb:         [PASS][3] -> [INCOMPLETE][4]
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9093/shard-iclb3/igt@kms_flip@flip-vs-suspend@c-edp1.html
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/shard-iclb3/igt@kms_flip@flip-vs-suspend@c-edp1.html

Looks like shard-iclb3 has a file system corruption, or just broken
storage device/host:
<3>[  240.012780] blk_update_request: I/O error, dev sda, sector 76863120 op 0x1:(WRITE) flags 0x800 phys_seg 10 prio class 0

This has been consistently happening now for a while on the shard-iclb3
machine leading to the same hang, see for instance
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9063/shard-iclb3/pstore7-1601302770_Panic_1.txt

Similar sporadic filesystem errors have been also happening on
shard-iclb4.

I haven't seen any recent I/O errors on any of the other 7 shard-icl
machines.

shard-iclb3/4 would probably need reinstall/new storage device/new host.

--Imre
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  reply	other threads:[~2020-10-03 13:49 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-03  0:18 [Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
2020-10-03  0:18 ` [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming Imre Deak
2020-10-05 20:08   ` Ville Syrjälä
2020-10-05 20:26     ` Imre Deak
2020-10-05 23:37       ` Ville Syrjälä
2020-10-06  1:24         ` Imre Deak
2020-10-06  1:35   ` [Intel-gfx] [PATCH v3 " Imre Deak
2020-10-06  8:59     ` Ville Syrjälä
2020-10-03  0:18 ` [Intel-gfx] [PATCH 2/5] drm/i915: Move the initial fastset commit check to encoder hooks Imre Deak
2020-10-03  1:07   ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-10-05 20:24     ` Ville Syrjälä
2020-10-05 20:34       ` Imre Deak
2020-10-05 21:53     ` [Intel-gfx] [PATCH v3 " Imre Deak
2020-10-06  9:42       ` Jani Nikula
2020-10-06  9:55         ` Imre Deak
2020-10-06 10:00           ` Jani Nikula
2020-10-06 10:05             ` Imre Deak
2020-10-03  0:18 ` [Intel-gfx] [PATCH 3/5] drm/i915: Check for unsupported DP link rates during initial commit Imre Deak
2020-10-05 20:25   ` Ville Syrjälä
2020-10-03  0:18 ` [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume Imre Deak
2020-10-05 20:30   ` Ville Syrjälä
2020-10-05 20:46     ` Imre Deak
2020-10-05 23:39       ` Ville Syrjälä
2020-10-05 20:40   ` Ville Syrjälä
2020-10-05 20:57     ` Imre Deak
2020-10-05 20:51   ` Ville Syrjälä
2020-10-05 23:00     ` Imre Deak
2020-10-05 21:53   ` [Intel-gfx] [PATCH v2 " Imre Deak
2020-10-05 23:01     ` [Intel-gfx] [PATCH v3 " Imre Deak
2020-10-06  8:58       ` Ville Syrjälä
2020-10-03  0:18 ` [Intel-gfx] [PATCH 5/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock Imre Deak
2020-10-03  0:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2) Patchwork
2020-10-03  0:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-03  1:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3) Patchwork
2020-10-03  1:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-03  3:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-10-03 13:48   ` Imre Deak [this message]
2020-10-04  6:12     ` Vudum, Lakshminarayana
2020-10-04  5:47 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2020-10-06  0:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) Patchwork
2020-10-06  0:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-06  1:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7) Patchwork
2020-10-06  2:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-06  2:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) Patchwork
2020-10-06 10:32   ` Imre Deak
2020-10-06 11:04     ` Imre Deak
2020-10-06  5:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7) Patchwork

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