From: Imre Deak <imre.deak@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 01/11] drm/i915: s/pre_empemph/preemph/
Date: Wed, 30 Sep 2020 16:56:00 +0300 [thread overview]
Message-ID: <20200930135600.GA867650@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <20200929233449.32323-2-ville.syrjala@linux.intel.com>
On Wed, Sep 30, 2020 at 02:34:39AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I managed to fumble some functions names. Fix them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 54a4b81ea3ff..ff96540c8612 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4167,12 +4167,12 @@ static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> }
>
> -static u8 intel_dp_pre_empemph_max_2(struct intel_dp *intel_dp)
> +static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
> {
> return DP_TRAIN_PRE_EMPH_LEVEL_2;
> }
>
> -static u8 intel_dp_pre_empemph_max_3(struct intel_dp *intel_dp)
> +static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
> {
> return DP_TRAIN_PRE_EMPH_LEVEL_3;
> }
> @@ -7953,10 +7953,10 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
> - dig_port->dp.preemph_max = intel_dp_pre_empemph_max_3;
> + dig_port->dp.preemph_max = intel_dp_preemph_max_3;
> dig_port->dp.voltage_max = intel_dp_voltage_max_3;
> } else {
> - dig_port->dp.preemph_max = intel_dp_pre_empemph_max_2;
> + dig_port->dp.preemph_max = intel_dp_preemph_max_2;
> dig_port->dp.voltage_max = intel_dp_voltage_max_2;
> }
>
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2020-09-30 13:56 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-29 23:34 [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjala
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 01/11] drm/i915: s/pre_empemph/preemph/ Ville Syrjala
2020-09-30 13:56 ` Imre Deak [this message]
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 02/11] drm/i915: s/old_crtc_state/crtc_state/ Ville Syrjala
2020-09-30 13:57 ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 03/11] drm/i915: Make intel_dp_process_phy_request() static Ville Syrjala
2020-09-30 13:58 ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 04/11] drm/i915: Shove the PHY test into the hotplug work Ville Syrjala
2020-09-30 8:10 ` kernel test robot
2020-09-30 10:04 ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2020-09-30 15:12 ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 05/11] drm/i915: Split ICL combo PHY buf trans per output type Ville Syrjala
2020-09-30 15:19 ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 06/11] drm/i915: Split ICL MG " Ville Syrjala
2020-09-30 15:21 ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 07/11] drm/i915: Split EHL combo " Ville Syrjala
2020-09-30 15:24 ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 08/11] drm/i915: Split TGL " Ville Syrjala
2020-09-30 15:29 ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 09/11] drm/i915: Split TGL DKL " Ville Syrjala
2020-09-30 15:31 ` Imre Deak
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 10/11] drm/i915: Plumb crtc_state to link training Ville Syrjala
2020-09-30 16:36 ` Imre Deak
2020-09-30 18:50 ` Ville Syrjälä
2020-10-01 11:10 ` [Intel-gfx] [PATCH v4 " Ville Syrjala
2020-09-29 23:34 ` [Intel-gfx] [PATCH v2 11/11] drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status} Ville Syrjala
2020-09-30 17:04 ` Imre Deak
2020-09-29 23:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev3) Patchwork
2020-09-29 23:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-09-30 0:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-30 10:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev4) Patchwork
2020-09-30 13:12 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plumb crtc state to link training code (rev3) Patchwork
2020-09-30 15:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Plumb crtc state to link training code (rev4) Patchwork
2020-10-01 11:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev5) Patchwork
2020-10-01 11:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-01 13:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-10-01 14:02 ` [Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code Ville Syrjälä
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