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* [Intel-gfx] [PATCH CI] drm/i915/display/ehl: Limit eDP to HBR2
@ 2020-10-05 17:54 José Roberto de Souza
  2020-10-05 20:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/ehl: Limit eDP to HBR2 (rev4) Patchwork
  2020-10-05 22:58 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  0 siblings, 2 replies; 3+ messages in thread
From: José Roberto de Souza @ 2020-10-05 17:54 UTC (permalink / raw)
  To: intel-gfx

Recent update in documentation defeatured eDP HBR3 for EHL and JSL.

v2:
- Remove dead code in ehl_get_combo_buf_trans()

v3:
- Rebase

BSpec: 32247
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Vidya Srinivas <vidya.srinivas@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  9 ++-------
 drivers/gpu/drm/i915/display/intel_dp.c  | 11 ++++++++++-
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b4c520348b3b..2c85d4202846 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1142,13 +1142,8 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	if (dev_priv->vbt.edp.low_vswing) {
-		if (crtc_state->port_clock > 540000) {
-			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
-			return icl_combo_phy_ddi_translations_edp_hbr3;
-		} else {
-			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
-			return icl_combo_phy_ddi_translations_edp_hbr2;
-		}
+		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
+		return icl_combo_phy_ddi_translations_edp_hbr2;
 	}
 
 	return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7429597b57be..4ae79e39c70c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -277,13 +277,20 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
 	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 
 	if (intel_phy_is_combo(dev_priv, phy) &&
-	    !IS_ELKHARTLAKE(dev_priv) &&
 	    !intel_dp_is_edp(intel_dp))
 		return 540000;
 
 	return 810000;
 }
 
+static int ehl_max_source_rate(struct intel_dp *intel_dp)
+{
+	if (intel_dp_is_edp(intel_dp))
+		return 540000;
+
+	return 810000;
+}
+
 static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
@@ -318,6 +325,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 		size = ARRAY_SIZE(cnl_rates);
 		if (IS_GEN(dev_priv, 10))
 			max_rate = cnl_max_source_rate(intel_dp);
+		else if (IS_ELKHARTLAKE(dev_priv))
+			max_rate = ehl_max_source_rate(intel_dp);
 		else
 			max_rate = icl_max_source_rate(intel_dp);
 	} else if (IS_GEN9_LP(dev_priv)) {
-- 
2.28.0

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^ permalink raw reply related	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-10-05 22:58 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-10-05 17:54 [Intel-gfx] [PATCH CI] drm/i915/display/ehl: Limit eDP to HBR2 José Roberto de Souza
2020-10-05 20:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/ehl: Limit eDP to HBR2 (rev4) Patchwork
2020-10-05 22:58 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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