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From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/3] drm/i915/skl: Move sanity check of WRPLL p1 divider value next to its read-out
Date: Tue,  6 Oct 2020 14:54:00 +0300	[thread overview]
Message-ID: <20201006115401.1521958-2-imre.deak@intel.com> (raw)
In-Reply-To: <20201006115401.1521958-1-imre.deak@intel.com>

Move the check of p1 divider value next to where it's read out.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 27a8c281382c..2a411dd46769 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1591,6 +1591,8 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
 	else
 		p1 = 1;
 
+	if (drm_WARN_ON(&i915->drm, p1 == 0))
+		return 0;
 
 	switch (p0) {
 	case DPLL_CFGCR2_PDIV_1:
@@ -1641,9 +1643,6 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
 	dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *
 		    ref_clock / 0x8000;
 
-	if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
-		return 0;
-
 	return dco_freq / (p0 * p1 * p2 * 5);
 }
 
-- 
2.25.1

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  reply	other threads:[~2020-10-06 11:54 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-06 11:53 [Intel-gfx] [PATCH 1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout Imre Deak
2020-10-06 11:54 ` Imre Deak [this message]
2020-10-06 11:54 ` [Intel-gfx] [PATCH 3/3] drm/i915/skl: Fix WRPLL p0/1/2 PDIV divider selection Imre Deak
2020-10-06 14:55 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout Patchwork

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