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From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 3/3] drm/i915/skl: Fix WRPLL p0/1/2 PDIV divider selection
Date: Tue,  6 Oct 2020 14:54:01 +0300	[thread overview]
Message-ID: <20201006115401.1521958-3-imre.deak@intel.com> (raw)
In-Reply-To: <20201006115401.1521958-1-imre.deak@intel.com>

The p0 divider (aka PDIV) doesn't support the div-by-5 configuration, so
in case the effective divider (p0*p1*p2) value is 5, either p1 (QDIV) or
p2 (KDIV) must be used. p1 can't be used either since it must match p0
if p0 is 1, so using p2 is the only possibility.

This didn't cause an actual problem, since the HDMI port clock is
limited to 300MHz on SKL, which means the minimum effective divider is 6
there, but let's still fix the logic (instead of removing dividers
smaller than 6 from the effective divider list).

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 2a411dd46769..eabe63716eb3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1367,8 +1367,12 @@ static void skl_wrpll_get_multipliers(unsigned int p,
 		*p0 = 3;
 		*p1 = 1;
 		*p2 = p / 3;
-	} else if (p == 5 || p == 7) {
-		*p0 = p;
+	} else if (p == 5) {
+		*p0 = 1;
+		*p1 = 1;
+		*p2 = 5;
+	} else if (p == 7) {
+		*p0 = 7;
 		*p1 = 1;
 		*p2 = 1;
 	} else if (p == 15) {
-- 
2.25.1

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  parent reply	other threads:[~2020-10-06 11:54 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-06 11:53 [Intel-gfx] [PATCH 1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout Imre Deak
2020-10-06 11:54 ` [Intel-gfx] [PATCH 2/3] drm/i915/skl: Move sanity check of WRPLL p1 divider value next to its read-out Imre Deak
2020-10-06 11:54 ` Imre Deak [this message]
2020-10-06 14:55 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/cnl: Handle incorrect divider values during WRPLL HW readout Patchwork

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