From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 7/8] drm/i915/dg1: Update comp master/slave relationships for PHYs
Date: Tue, 6 Oct 2020 17:22:09 -0700 [thread overview]
Message-ID: <20201007002210.3678024-7-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20201007002210.3678024-1-lucas.demarchi@intel.com>
From: Matt Roper <matthew.d.roper@intel.com>
As with RKL, DG1's PHY C acts as a comp master for PHY D.
Bspec: 49291
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 07c9fa2fb835..932265f1ac90 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -243,14 +243,14 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
*
* ICL,TGL:
* A(master) -> B(slave), C(slave)
- * RKL:
+ * RKL,DG1:
* A(master) -> B(slave)
* C(master) -> D(slave)
*
* We must set the IREFGEN bit for any PHY acting as a master
* to another PHY.
*/
- if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
+ if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C)
return true;
return phy == PHY_A;
--
2.28.0
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next prev parent reply other threads:[~2020-10-07 0:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-07 0:22 [Intel-gfx] [CI 1/8] drm/i915/dg1: add more PCI ids Lucas De Marchi
2020-10-07 0:22 ` [Intel-gfx] [CI 2/8] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-10-07 0:22 ` [Intel-gfx] [CI 3/8] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-10-07 0:22 ` [Intel-gfx] [CI 4/8] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-10-07 0:22 ` [Intel-gfx] [CI 5/8] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-10-07 0:22 ` [Intel-gfx] [CI 6/8] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-10-07 0:22 ` Lucas De Marchi [this message]
2020-10-07 0:22 ` [Intel-gfx] [CI 8/8] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-10-07 0:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/8] drm/i915/dg1: add more PCI ids Patchwork
2020-10-07 16:09 ` Lucas De Marchi
2020-10-07 1:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-07 2:21 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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