From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 8/8] drm/i915/dg1: provide port/phy mapping for vbt
Date: Tue, 6 Oct 2020 17:22:10 -0700 [thread overview]
Message-ID: <20201007002210.3678024-8-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20201007002210.3678024-1-lucas.demarchi@intel.com>
From: Matt Roper <matthew.d.roper@intel.com>
As with RKL, DG1's VBT outputs are indexed according to PHY rather than
DDI.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 23bf21ee58ea..5804eb9faf24 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1675,7 +1675,7 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
};
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
ARRAY_SIZE(rkl_port_mapping[0]),
rkl_port_mapping,
@@ -2640,10 +2640,12 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
aux_ch = AUX_CH_B;
break;
case DP_AUX_C:
- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
+ aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
+ AUX_CH_D : AUX_CH_C;
break;
case DP_AUX_D:
- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
+ aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
+ AUX_CH_E : AUX_CH_D;
break;
case DP_AUX_E:
aux_ch = AUX_CH_E;
--
2.28.0
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next prev parent reply other threads:[~2020-10-07 0:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-07 0:22 [Intel-gfx] [CI 1/8] drm/i915/dg1: add more PCI ids Lucas De Marchi
2020-10-07 0:22 ` [Intel-gfx] [CI 2/8] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-10-07 0:22 ` [Intel-gfx] [CI 3/8] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-10-07 0:22 ` [Intel-gfx] [CI 4/8] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-10-07 0:22 ` [Intel-gfx] [CI 5/8] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-10-07 0:22 ` [Intel-gfx] [CI 6/8] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-10-07 0:22 ` [Intel-gfx] [CI 7/8] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-10-07 0:22 ` Lucas De Marchi [this message]
2020-10-07 0:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/8] drm/i915/dg1: add more PCI ids Patchwork
2020-10-07 16:09 ` Lucas De Marchi
2020-10-07 1:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-07 2:21 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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