From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Fix MOCS PTE setting for gen9+
Date: Wed, 7 Oct 2020 15:03:28 +0300 [thread overview]
Message-ID: <20201007120329.17076-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20201007120329.17076-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fix up the MOCS PTE setting to really get the LLC cacheability
from the PTE rather than hardocoding it to LLC or LLC+eLLC.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 632e08a4592b..6f771a482608 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -124,7 +124,7 @@ struct drm_i915_mocs_table {
LE_1_UC | LE_TC_2_LLC_ELLC, \
L3_1_UC), \
MOCS_ENTRY(I915_MOCS_PTE, \
- LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), \
+ LE_0_PAGETABLE | LE_TC_0_PAGETABLE | LE_LRUM(3), \
L3_3_WB)
static const struct drm_i915_mocs_entry skl_mocs_table[] = {
@@ -274,7 +274,7 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
L3_1_UC),
/* Base - L3 + LeCC:PAT (Deprecated) */
MOCS_ENTRY(I915_MOCS_PTE,
- LE_0_PAGETABLE | LE_TC_1_LLC,
+ LE_0_PAGETABLE | LE_TC_0_PAGETABLE,
L3_3_WB),
GEN11_MOCS_ENTRIES
--
2.26.2
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next prev parent reply other threads:[~2020-10-07 12:03 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-07 12:03 [Intel-gfx] [PATCH 1/3] drm/i915: Mark ininitial fb obj as WT on eLLC machines to avoid rcu lockup during fbdev init Ville Syrjala
2020-10-07 12:03 ` Ville Syrjala [this message]
2020-10-13 15:51 ` [Intel-gfx] [PATCH 2/3] drm/i915: Fix MOCS PTE setting for gen9+ Chris Wilson
2020-10-13 16:11 ` Ville Syrjälä
2020-10-07 12:03 ` [Intel-gfx] [PATCH 3/3] drm/i915: Enable eLLC caching of display buffers for SKL+ Ville Syrjala
2020-10-07 13:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Mark ininitial fb obj as WT on eLLC machines to avoid rcu lockup during fbdev init Patchwork
2020-10-13 15:47 ` [Intel-gfx] [PATCH 1/3] " Chris Wilson
2020-10-13 16:12 ` Ville Syrjälä
2020-10-13 19:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Mark ininitial fb obj as WT on eLLC machines to avoid rcu lockup during fbdev init (rev2) Patchwork
2020-10-14 14:23 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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