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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915: Fix MOCS PTE setting for gen9+
Date: Tue, 13 Oct 2020 19:11:12 +0300	[thread overview]
Message-ID: <20201013161112.GC6112@intel.com> (raw)
In-Reply-To: <160260426090.2946.5418082025217279551@build.alporthouse.com>

On Tue, Oct 13, 2020 at 04:51:00PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2020-10-07 13:03:28)
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Fix up the MOCS PTE setting to really get the LLC cacheability
> > from the PTE rather than hardocoding it to LLC or LLC+eLLC.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_mocs.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > index 632e08a4592b..6f771a482608 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > @@ -124,7 +124,7 @@ struct drm_i915_mocs_table {
> >                    LE_1_UC | LE_TC_2_LLC_ELLC, \
> >                    L3_1_UC), \
> >         MOCS_ENTRY(I915_MOCS_PTE, \
> > -                  LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), \
> > +                  LE_0_PAGETABLE | LE_TC_0_PAGETABLE | LE_LRUM(3), \
> >                    L3_3_WB)
> >  
> >  static const struct drm_i915_mocs_entry skl_mocs_table[] = {
> > @@ -274,7 +274,7 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
> >                    L3_1_UC),
> >         /* Base - L3 + LeCC:PAT (Deprecated) */
> >         MOCS_ENTRY(I915_MOCS_PTE,
> > -                  LE_0_PAGETABLE | LE_TC_1_LLC,
> > +                  LE_0_PAGETABLE | LE_TC_0_PAGETABLE,
> >                    L3_3_WB),
> 
> Makes sense. Did the PAGETABLE bit carry forward into tgl? That might
> fixup the new regression...

At least I still see it in the docs. What troubles me here is the
"deprecated" comment someone added. If this is deprecated how are we
supposed to configure cachine for display surfaces?

> 
> For the two given here, it certainly exists and makes a whole lot of
> sense,
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> -Chris

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2020-10-13 16:11 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-07 12:03 [Intel-gfx] [PATCH 1/3] drm/i915: Mark ininitial fb obj as WT on eLLC machines to avoid rcu lockup during fbdev init Ville Syrjala
2020-10-07 12:03 ` [Intel-gfx] [PATCH 2/3] drm/i915: Fix MOCS PTE setting for gen9+ Ville Syrjala
2020-10-13 15:51   ` Chris Wilson
2020-10-13 16:11     ` Ville Syrjälä [this message]
2020-10-07 12:03 ` [Intel-gfx] [PATCH 3/3] drm/i915: Enable eLLC caching of display buffers for SKL+ Ville Syrjala
2020-10-07 13:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Mark ininitial fb obj as WT on eLLC machines to avoid rcu lockup during fbdev init Patchwork
2020-10-13 15:47 ` [Intel-gfx] [PATCH 1/3] " Chris Wilson
2020-10-13 16:12   ` Ville Syrjälä
2020-10-13 19:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Mark ininitial fb obj as WT on eLLC machines to avoid rcu lockup during fbdev init (rev2) Patchwork
2020-10-14 14:23 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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