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From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris.p.wilson@intel.com>
Subject: [Intel-gfx] [PATCH 1/6] drm/i915/perf: Ensure observation logic is not clock gated
Date: Fri,  9 Oct 2020 17:21:00 -0700	[thread overview]
Message-ID: <20201010002105.45152-2-umesh.nerlige.ramappa@intel.com> (raw)
In-Reply-To: <20201010002105.45152-1-umesh.nerlige.ramappa@intel.com>

From: Piotr Maciejewski <piotr.maciejewski@intel.com>

A clock gating switch can control if the performance monitoring and
observation logic is enaled or not. Ensure that we enable the clocks.

v2: Separate code from other patches (Lionel)
v3: Reset PMON enable when disabling perf to save power (Lionel)
v4: Use intel_uncore_rmw and REG_BIT (Chris)

Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c | 9 +++++++++
 drivers/gpu/drm/i915/i915_reg.h  | 2 ++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e94976976571..df5166d89d82 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2520,6 +2520,12 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
 			    (period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
 			    : 0);
 
+	/*
+	 * Initialize Super Queue Internal Cnt Register
+	 * Set PMON Enable in order to collect valid metrics.
+	 */
+	intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, GEN12_SQCNT1_PMON_ENABLE);
+
 	/*
 	 * Update all contexts prior writing the mux configurations as we need
 	 * to make sure all slices/subslices are ON before writing to NOA
@@ -2579,6 +2585,9 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream)
 
 	/* Make sure we disable noa to save power. */
 	intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
+
+	/* Reset PMON Enable to save power. */
+	intel_uncore_rmw(uncore, GEN12_SQCNT1, GEN12_SQCNT1_PMON_ENABLE, 0);
 }
 
 static void gen7_oa_enable(struct i915_perf_stream *stream)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6ad9ee4243a0..558df3838069 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -696,6 +696,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define OABUFFER_SIZE_16M   (7 << 3)
 
 #define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
+#define GEN12_SQCNT1 _MMIO(0x8718)
+#define  GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
 
 /* Gen12 OAR unit */
 #define GEN12_OAR_OACONTROL _MMIO(0x2960)
-- 
2.20.1

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  reply	other threads:[~2020-10-10  0:21 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-10  0:20 [Intel-gfx] [PATCH 0/6] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-10-10  0:21 ` Umesh Nerlige Ramappa [this message]
2020-10-10  0:21 ` [Intel-gfx] [PATCH 2/6] drm/i915/gt: Lock intel_engine_apply_whitelist with uncore->lock Umesh Nerlige Ramappa
2020-11-12 19:37   ` Chris Wilson
2020-10-10  0:21 ` [Intel-gfx] [PATCH 3/6] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
2020-10-10  0:21 ` [Intel-gfx] [PATCH 4/6] drm/i915/gt: Refactor _wa_add to reuse wa_index and wa_list_grow Umesh Nerlige Ramappa
2020-11-12 19:44   ` Chris Wilson
2020-11-13 10:40     ` Tvrtko Ursulin
2020-11-13 11:02       ` Chris Wilson
2020-10-10  0:21 ` [Intel-gfx] [PATCH 5/6] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
2020-10-10  0:21 ` [Intel-gfx] [PATCH 6/6] drm/i915/perf: Map OA buffer to user space for gen12 performance query Umesh Nerlige Ramappa
2020-10-10  0:53 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Allow privileged user to map the OA buffer Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2020-10-02 23:27 [Intel-gfx] [PATCH 0/6] " Umesh Nerlige Ramappa
2020-10-02 23:27 ` [Intel-gfx] [PATCH 1/6] drm/i915/perf: Ensure observation logic is not clock gated Umesh Nerlige Ramappa

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