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From: Chris Wilson <chris@chris-wilson.co.uk>
To: igt-dev@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org, Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH i-g-t 08/10] lib: Use unsigned gen for forward compatible tests
Date: Wed, 14 Oct 2020 11:40:36 +0100	[thread overview]
Message-ID: <20201014104038.2554985-8-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20201014104038.2554985-1-chris@chris-wilson.co.uk>

Unknown, so future, gen are marked as -1 which we want to treat as -1u
so that always pass >= gen checks.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2298
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_batchbuffer.c | 10 +++++-----
 lib/intel_batchbuffer.h | 10 ++++++----
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 60dbfe261..fc73495c0 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -414,7 +414,7 @@ intel_blt_copy(struct intel_batchbuffer *batch,
 	       drm_intel_bo *dst_bo, int dst_x1, int dst_y1, int dst_pitch,
 	       int width, int height, int bpp)
 {
-	const int gen = batch->gen;
+	const unsigned int gen = batch->gen;
 	uint32_t src_tiling, dst_tiling, swizzle;
 	uint32_t cmd_bits = 0;
 	uint32_t br13_bits;
@@ -553,7 +553,7 @@ unsigned igt_buf_height(const struct igt_buf *buf)
  * Returns:
  * The width of the ccs buffer data.
  */
-unsigned int igt_buf_intel_ccs_width(int gen, const struct igt_buf *buf)
+unsigned int igt_buf_intel_ccs_width(unsigned int gen, const struct igt_buf *buf)
 {
 	/*
 	 * GEN12+: The CCS unit size is 64 bytes mapping 4 main surface
@@ -576,7 +576,7 @@ unsigned int igt_buf_intel_ccs_width(int gen, const struct igt_buf *buf)
  * Returns:
  * The height of the ccs buffer data.
  */
-unsigned int igt_buf_intel_ccs_height(int gen, const struct igt_buf *buf)
+unsigned int igt_buf_intel_ccs_height(unsigned int gen, const struct igt_buf *buf)
 {
 	/*
 	 * GEN12+: The CCS unit size is 64 bytes mapping 4 main surface
@@ -703,7 +703,7 @@ fill_object(struct drm_i915_gem_exec_object2 *obj, uint32_t gem_handle,
 
 static void exec_blit(int fd,
 		      struct drm_i915_gem_exec_object2 *objs, uint32_t count,
-		      int gen)
+		      unsigned int gen)
 {
 	struct drm_i915_gem_execbuffer2 exec = {
 		.buffers_ptr = to_user_pointer(objs),
@@ -2416,7 +2416,7 @@ void intel_bb_emit_blt_copy(struct intel_bb *ibb,
 			    int dst_x1, int dst_y1, int dst_pitch,
 			    int width, int height, int bpp)
 {
-	const int gen = ibb->gen;
+	const unsigned int gen = ibb->gen;
 	uint32_t cmd_bits = 0;
 	uint32_t br13_bits;
 	uint32_t mask;
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index d20b4e66a..ab1b0c286 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -15,7 +15,7 @@
 struct intel_batchbuffer {
 	drm_intel_bufmgr *bufmgr;
 	uint32_t devid;
-	int gen;
+	unsigned int gen;
 
 	drm_intel_context *ctx;
 	drm_intel_bo *bo;
@@ -263,8 +263,10 @@ static inline bool igt_buf_compressed(const struct igt_buf *buf)
 
 unsigned igt_buf_width(const struct igt_buf *buf);
 unsigned igt_buf_height(const struct igt_buf *buf);
-unsigned int igt_buf_intel_ccs_width(int gen, const struct igt_buf *buf);
-unsigned int igt_buf_intel_ccs_height(int gen, const struct igt_buf *buf);
+unsigned int igt_buf_intel_ccs_width(unsigned int gen,
+				     const struct igt_buf *buf);
+unsigned int igt_buf_intel_ccs_height(unsigned int gen,
+				      const struct igt_buf *buf);
 
 void igt_blitter_src_copy(int fd,
 			  /* src */
@@ -434,7 +436,7 @@ igt_media_spinfunc_t igt_get_media_spinfunc(int devid);
  */
 struct intel_bb {
 	int i915;
-	int gen;
+	unsigned int gen;
 	bool debug;
 	bool dump_base64;
 	bool enforce_relocs;
-- 
2.28.0

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  parent reply	other threads:[~2020-10-14 10:41 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-14 10:40 [Intel-gfx] [PATCH i-g-t 01/10] i915/gem_userptr_blits: Tighten has_userptr() Chris Wilson
2020-10-14 10:40 ` [Intel-gfx] [PATCH i-g-t 02/10] i915/gem_exec_balancer: Check balancer submission latency Chris Wilson
2020-10-14 10:40 ` [Intel-gfx] [PATCH i-g-t 03/10] i915/gen9_exec_parse: Check oversized batch with length==0 Chris Wilson
2020-10-14 10:43   ` Matthew Auld
2020-10-14 10:49     ` [Intel-gfx] [igt-dev] " Chris Wilson
2020-10-14 10:40 ` [Intel-gfx] [PATCH i-g-t 04/10] i915/gem_exec_schedule: Include userptr scheduling tests Chris Wilson
2020-10-14 10:40 ` [Intel-gfx] [PATCH i-g-t 05/10] i915/gem_exec_balancer: Check interactions between bonds and userptr Chris Wilson
2020-10-14 10:40 ` [Intel-gfx] [PATCH i-g-t 06/10] i915/gem_exec_reloc: Continuing the trend of checking userptr Chris Wilson
2020-10-14 10:40 ` [Intel-gfx] [PATCH i-g-t 07/10] i915/gem_userptr_blits: Test execution isolation Chris Wilson
2020-10-14 10:40 ` Chris Wilson [this message]
2020-10-15  4:58   ` [Intel-gfx] [PATCH i-g-t 08/10] lib: Use unsigned gen for forward compatible tests Zbigniew Kempczyński
2020-10-14 10:40 ` [Intel-gfx] [PATCH i-g-t 09/10] tests/i915: Treat gen as unsigned for forward compatibility Chris Wilson
2020-10-14 10:40 ` [Intel-gfx] [PATCH i-g-t 10/10] i915/gem_exec_schedule: Try to spot unfairness Chris Wilson
2020-10-15 12:53 ` [Intel-gfx] [igt-dev] [PATCH i-g-t 01/10] i915/gem_userptr_blits: Tighten has_userptr() Tvrtko Ursulin

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