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From: Imre Deak <imre.deak@intel.com>
To: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Cc: intel-gfx@lists.freedesktop.org, hariom.pandey@intel.com
Subject: Re: [Intel-gfx] [PATCH] drm/i915/ehl: Implement W/A 22010492432
Date: Wed, 28 Oct 2020 19:40:35 +0200	[thread overview]
Message-ID: <20201028174035.GD3693479@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <20201028091641.137195-1-tejaskumarx.surendrakumar.upadhyay@intel.com>

On Wed, Oct 28, 2020 at 02:46:41PM +0530, Tejas Upadhyay wrote:
> As per W/A implemented for TGL to program half of the nominal
> DCO divider fraction value which is also applicable on EHL.
> 
> Cc: Deak Imre <imre.deak@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 12 +++++++-----
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index eaef7a2d041f..0f3208d3c083 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2636,13 +2636,15 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
>  }
>  
>  /*
> - * Display WA #22010492432: tgl
> + * Display WA #22010492432: ehl, tgl
>   * Program half of the nominal DCO divider fraction value.
>   */
>  static bool
> -tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
> +combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)

The usual way is to prefix such function names with the earliest
relevant platform, so I'd use ehl_ here.

>  {
> -	return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;
> +	return (IS_PLATFORM(i915, INTEL_ELKHARTLAKE) ||

On EHL the WA is needed only B stepping onwards.

> +		IS_TIGERLAKE(i915)) &&
> +		i915->dpll.ref_clks.nssc == 38400;
>  }
>  
>  static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> @@ -2696,7 +2698,7 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
>  	dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
>  		       DPLL_CFGCR0_DCO_FRACTION_SHIFT;
>  
> -	if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
> +	if (combo_pll_div_frac_wa_needed(dev_priv))
>  		dco_fraction *= 2;
>  
>  	dco_freq += (dco_fraction * ref_clock) / 0x8000;
> @@ -3086,7 +3088,7 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
>  
>  	memset(pll_state, 0, sizeof(*pll_state));
>  
> -	if (tgl_combo_pll_div_frac_wa_needed(i915))
> +	if (combo_pll_div_frac_wa_needed(i915))
>  		dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
>  
>  	pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
> -- 
> 2.28.0
> 
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      parent reply	other threads:[~2020-10-28 17:40 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-28  9:16 [Intel-gfx] [PATCH] drm/i915/ehl: Implement W/A 22010492432 Tejas Upadhyay
2020-10-28 10:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2020-10-28 12:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-10-28 17:40 ` Imre Deak [this message]

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