[Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode

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* [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes
@ 2020-11-02 21:19 Manasi Navare
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 2/6] drm/i915: Move encoder->get_config to a new function Manasi Navare
                   ` (15 more replies)
  0 siblings, 16 replies; 32+ messages in thread
From: Manasi Navare @ 2020-11-02 21:19 UTC (permalink / raw)
  To: intel-gfx

No functional changes. This patch just moves some mode checks
around to prepare for adding bigjoiner related mode validation

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cf09aca7607b..ca4d4a8122d9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -721,6 +721,9 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
 
+	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+		return MODE_H_ILLEGAL;
+
 	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 		if (mode->hdisplay > fixed_mode->hdisplay)
 			return MODE_PANEL;
@@ -731,6 +734,9 @@ intel_dp_mode_valid(struct drm_connector *connector,
 		target_clock = fixed_mode->clock;
 	}
 
+	if (mode->clock < 10000)
+		return MODE_CLOCK_LOW;
+
 	max_link_clock = intel_dp_max_link_rate(intel_dp);
 	max_lanes = intel_dp_max_lane_count(intel_dp);
 
@@ -771,12 +777,6 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	    target_clock > max_dotclk)
 		return MODE_CLOCK_HIGH;
 
-	if (mode->clock < 10000)
-		return MODE_CLOCK_LOW;
-
-	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
-		return MODE_H_ILLEGAL;
-
 	status = intel_dp_mode_valid_downstream(intel_connector,
 						mode, target_clock);
 	if (status != MODE_OK)
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread

* [Intel-gfx] [PATCH v5 2/6] drm/i915: Move encoder->get_config to a new function
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
@ 2020-11-02 21:19 ` Manasi Navare
  2020-11-05 15:15   ` Ville Syrjälä
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 3/6] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split Manasi Navare
                   ` (14 subsequent siblings)
  15 siblings, 1 reply; 32+ messages in thread
From: Manasi Navare @ 2020-11-02 21:19 UTC (permalink / raw)
  To: intel-gfx

No functional changes, create a separate intel_encoder_get_config()
function that calls encoder->get_config hook.
This is needed so that later we can add beigjoienr related
readout here.

Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cddbda5303ff..e9fbcfe1649e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8222,6 +8222,12 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
 		       pfit_w * pfit_h);
 }
 
+static void intel_encoder_get_config(struct intel_encoder *encoder,
+				     struct intel_crtc_state *crtc_state)
+{
+	encoder->get_config(encoder, crtc_state);
+}
+
 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
@@ -12475,7 +12481,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
 		return NULL;
 	}
 
-	encoder->get_config(encoder, crtc_state);
+	intel_encoder_get_config(encoder, crtc_state);
 
 	intel_mode_from_pipe_config(mode, crtc_state);
 
@@ -14520,7 +14526,7 @@ verify_crtc_state(struct intel_crtc *crtc,
 				pipe_name(pipe));
 
 		if (active)
-			encoder->get_config(encoder, pipe_config);
+			intel_encoder_get_config(encoder, pipe_config);
 	}
 
 	intel_crtc_compute_pixel_rate(pipe_config);
@@ -18835,7 +18841,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			crtc_state = to_intel_crtc_state(crtc->base.state);
 
 			encoder->base.crtc = &crtc->base;
-			encoder->get_config(encoder, crtc_state);
+			intel_encoder_get_config(encoder, crtc_state);
 			if (encoder->sync_state)
 				encoder->sync_state(encoder, crtc_state);
 		} else {
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread

* Re: [Intel-gfx] [PATCH v5 2/6] drm/i915: Move encoder->get_config to a new function
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 2/6] drm/i915: Move encoder->get_config to a new function Manasi Navare
@ 2020-11-05 15:15   ` Ville Syrjälä
  0 siblings, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2020-11-05 15:15 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx

On Mon, Nov 02, 2020 at 01:19:02PM -0800, Manasi Navare wrote:
> No functional changes, create a separate intel_encoder_get_config()
> function that calls encoder->get_config hook.
> This is needed so that later we can add beigjoienr related
> readout here.
> 
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index cddbda5303ff..e9fbcfe1649e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8222,6 +8222,12 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
>  		       pfit_w * pfit_h);
>  }
>  
> +static void intel_encoder_get_config(struct intel_encoder *encoder,
> +				     struct intel_crtc_state *crtc_state)
> +{
> +	encoder->get_config(encoder, crtc_state);
> +}
> +
>  static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> @@ -12475,7 +12481,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
>  		return NULL;
>  	}
>  
> -	encoder->get_config(encoder, crtc_state);
> +	intel_encoder_get_config(encoder, crtc_state);
>  
>  	intel_mode_from_pipe_config(mode, crtc_state);
>  
> @@ -14520,7 +14526,7 @@ verify_crtc_state(struct intel_crtc *crtc,
>  				pipe_name(pipe));
>  
>  		if (active)
> -			encoder->get_config(encoder, pipe_config);
> +			intel_encoder_get_config(encoder, pipe_config);
>  	}
>  
>  	intel_crtc_compute_pixel_rate(pipe_config);
> @@ -18835,7 +18841,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  			crtc_state = to_intel_crtc_state(crtc->base.state);
>  
>  			encoder->base.crtc = &crtc->base;
> -			encoder->get_config(encoder, crtc_state);
> +			intel_encoder_get_config(encoder, crtc_state);
>  			if (encoder->sync_state)
>  				encoder->sync_state(encoder, crtc_state);
>  		} else {
> -- 
> 2.19.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] [PATCH v5 3/6] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 2/6] drm/i915: Move encoder->get_config to a new function Manasi Navare
@ 2020-11-02 21:19 ` Manasi Navare
  2020-11-02 23:04   ` [Intel-gfx] [PATCH v6 " Manasi Navare
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 4/6] drm/i915: Pass intel_atomic_state instead of drm_atomic_state Manasi Navare
                   ` (13 subsequent siblings)
  15 siblings, 1 reply; 32+ messages in thread
From: Manasi Navare @ 2020-11-02 21:19 UTC (permalink / raw)
  To: intel-gfx

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
because of this, we need a pipe_mode for various calculations, including
for example watermarks, plane clipping, etc.

v9:
* pipe_mode in state dump nd state check (Ville)
v8:
* Add pipe_mode in readout in verify_crtc_state (Ville)
v7:
* Remove redundant comment (Ville)
* Just keep mode instead of pipe_mode (Ville)
v6:
* renaming in separate function, only pipe_mode here (Ville)
* Add description (Maarten)
v5:
* Rebase (Manasi)
v4:
* Manual rebase (Manasi)
v3:
* Change state to crtc_state, fix rebase err  (Manasi)
v2:
* Manual Rebase (Manasi)

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 49 +++++++-----
 .../drm/i915/display/intel_display_types.h    | 11 ++-
 drivers/gpu/drm/i915/intel_pm.c               | 76 +++++++++----------
 3 files changed, 79 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e9fbcfe1649e..e8cdfab69c91 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6167,18 +6167,16 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 
 static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
 {
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
+	const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
 	int width, height;
 
 	if (crtc_state->pch_pfit.enabled) {
 		width = drm_rect_width(&crtc_state->pch_pfit.dst);
 		height = drm_rect_height(&crtc_state->pch_pfit.dst);
 	} else {
-		width = adjusted_mode->crtc_hdisplay;
-		height = adjusted_mode->crtc_vdisplay;
+		width = pipe_mode->crtc_hdisplay;
+		height = pipe_mode->crtc_vdisplay;
 	}
-
 	return skl_update_scaler(crtc_state, !crtc_state->hw.active,
 				 SKL_CRTC_INDEX,
 				 &crtc_state->scaler_state.scaler_id,
@@ -8192,7 +8190,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
 
 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
 {
-	u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
+	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
 	unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
 
 	/*
@@ -8225,7 +8223,11 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
 static void intel_encoder_get_config(struct intel_encoder *encoder,
 				     struct intel_crtc_state *crtc_state)
 {
+	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
+
 	encoder->get_config(encoder, crtc_state);
+
+	*pipe_mode = crtc_state->hw.adjusted_mode;
 }
 
 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
@@ -8235,7 +8237,7 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
 	if (HAS_GMCH(dev_priv))
 		/* FIXME calculate proper pipe pixel rate for GMCH pfit */
 		crtc_state->pixel_rate =
-			crtc_state->hw.adjusted_mode.crtc_clock;
+			crtc_state->hw.pipe_mode.crtc_clock;
 	else
 		crtc_state->pixel_rate =
 			ilk_pipe_pixel_rate(crtc_state);
@@ -8245,7 +8247,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 				     struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+	const struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
 	int clock_limit = dev_priv->max_dotclk_freq;
 
 	if (INTEL_GEN(dev_priv) < 4) {
@@ -8256,16 +8258,16 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 		 * is > 90% of the (display) core speed.
 		 */
 		if (intel_crtc_supports_double_wide(crtc) &&
-		    adjusted_mode->crtc_clock > clock_limit) {
+		    pipe_mode->crtc_clock > clock_limit) {
 			clock_limit = dev_priv->max_dotclk_freq;
 			pipe_config->double_wide = true;
 		}
 	}
 
-	if (adjusted_mode->crtc_clock > clock_limit) {
+	if (pipe_mode->crtc_clock > clock_limit) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
-			    adjusted_mode->crtc_clock, clock_limit,
+			    pipe_mode->crtc_clock, clock_limit,
 			    yesno(pipe_config->double_wide));
 		return -EINVAL;
 	}
@@ -8308,7 +8310,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
 	 */
 	if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
-		adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
+		pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
 		return -EINVAL;
 
 	intel_crtc_compute_pixel_rate(pipe_config);
@@ -12827,15 +12829,15 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
 
 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
 {
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
+	const struct drm_display_mode *pipe_mode =
+		&crtc_state->hw.pipe_mode;
 	int linetime_wm;
 
 	if (!crtc_state->hw.enable)
 		return 0;
 
-	linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
-					adjusted_mode->crtc_clock);
+	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
+					pipe_mode->crtc_clock);
 
 	return min(linetime_wm, 0x1ff);
 }
@@ -13322,7 +13324,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
 	drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
 	drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
+	drm_dbg_kms(&dev_priv->drm, "pipe mode:\n");
+	drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode);
 	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
+	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
 	drm_dbg_kms(&dev_priv->drm,
 		    "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
 		    pipe_config->port_clock,
@@ -13465,8 +13470,9 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
 	crtc_state->hw.enable = crtc_state->uapi.enable;
 	crtc_state->hw.active = crtc_state->uapi.active;
 	crtc_state->hw.mode = crtc_state->uapi.mode;
-	crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
+	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
 	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
+
 	intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
 }
 
@@ -13663,6 +13669,9 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
 		    "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
 		    base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
 
+	/* without bigjoiner, pipe_mode == adjusted_mode */
+	pipe_config->hw.pipe_mode = pipe_config->hw.adjusted_mode;
+
 	return 0;
 }
 
@@ -14071,6 +14080,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 	PIPE_CONF_CHECK_X(output_types);
 
+	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
+	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
+	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
+	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
 	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
 	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
 	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
@@ -18920,6 +18933,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			 */
 			crtc_state->inherited = true;
 
+			crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode;
+
 			intel_crtc_compute_pixel_rate(crtc_state);
 
 			intel_crtc_update_active_timings(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f6f0626649e0..b526afee595c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -817,15 +817,22 @@ struct intel_crtc_state {
 	 * The following members are used to verify the hardware state:
 	 * - enable
 	 * - active
-	 * - mode / adjusted_mode
+	 * - mode/adjusted_mode
 	 * - color property blobs.
 	 *
 	 * During initial hw readout, they need to be copied to uapi.
+	 *
+	 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
+	 * Use the pipe_mode for calculations like watermarks, pipe
+	 * scaler, and bandwidth.
+	 *
+	 * Use adjusted_mode for things that need to know the full
+	 * mode on the transcoder, which spans all pipes.
 	 */
 	struct {
 		bool active, enable;
 		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
-		struct drm_display_mode mode, adjusted_mode;
+		struct drm_display_mode mode, pipe_mode, adjusted_mode;
 		enum drm_scaling_filter scaling_filter;
 	} hw;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f54375b11964..9898c257d3e0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -899,12 +899,12 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc)
 
 	crtc = single_enabled_crtc(dev_priv);
 	if (crtc) {
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->hw.adjusted_mode;
+		const struct drm_display_mode *pipe_mode =
+			&crtc->config->hw.pipe_mode;
 		const struct drm_framebuffer *fb =
 			crtc->base.primary->state->fb;
 		int cpp = fb->format->cpp[0];
-		int clock = adjusted_mode->crtc_clock;
+		int clock = pipe_mode->crtc_clock;
 
 		/* Display SR */
 		wm = intel_calculate_wm(clock, &pnv_display_wm,
@@ -1135,8 +1135,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
+	const struct drm_display_mode *pipe_mode =
+		&crtc_state->hw.pipe_mode;
 	unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
 	unsigned int clock, htotal, cpp, width, wm;
 
@@ -1163,8 +1163,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
 	    level != G4X_WM_LEVEL_NORMAL)
 		cpp = max(cpp, 4u);
 
-	clock = adjusted_mode->crtc_clock;
-	htotal = adjusted_mode->crtc_htotal;
+	clock = pipe_mode->crtc_clock;
+	htotal = pipe_mode->crtc_htotal;
 
 	width = drm_rect_width(&plane_state->uapi.dst);
 
@@ -1660,8 +1660,8 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
+	const struct drm_display_mode *pipe_mode =
+		&crtc_state->hw.pipe_mode;
 	unsigned int clock, htotal, cpp, width, wm;
 
 	if (dev_priv->wm.pri_latency[level] == 0)
@@ -1671,8 +1671,8 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
 		return 0;
 
 	cpp = plane_state->hw.fb->format->cpp[0];
-	clock = adjusted_mode->crtc_clock;
-	htotal = adjusted_mode->crtc_htotal;
+	clock = pipe_mode->crtc_clock;
+	htotal = pipe_mode->crtc_htotal;
 	width = crtc_state->pipe_src_w;
 
 	if (plane->id == PLANE_CURSOR) {
@@ -2261,12 +2261,12 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
 	if (crtc) {
 		/* self-refresh has much higher latency */
 		static const int sr_latency_ns = 12000;
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->hw.adjusted_mode;
+		const struct drm_display_mode *pipe_mode =
+			&crtc->config->hw.pipe_mode;
 		const struct drm_framebuffer *fb =
 			crtc->base.primary->state->fb;
-		int clock = adjusted_mode->crtc_clock;
-		int htotal = adjusted_mode->crtc_htotal;
+		int clock = pipe_mode->crtc_clock;
+		int htotal = pipe_mode->crtc_htotal;
 		int hdisplay = crtc->config->pipe_src_w;
 		int cpp = fb->format->cpp[0];
 		int entries;
@@ -2345,8 +2345,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
 	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
 	if (intel_crtc_active(crtc)) {
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->hw.adjusted_mode;
+		const struct drm_display_mode *pipe_mode =
+			&crtc->config->hw.pipe_mode;
 		const struct drm_framebuffer *fb =
 			crtc->base.primary->state->fb;
 		int cpp;
@@ -2356,7 +2356,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 		else
 			cpp = fb->format->cpp[0];
 
-		planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
+		planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
 					       wm_info, fifo_size, cpp,
 					       pessimal_latency_ns);
 		enabled = crtc;
@@ -2372,8 +2372,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
 	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
 	if (intel_crtc_active(crtc)) {
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->hw.adjusted_mode;
+		const struct drm_display_mode *pipe_mode =
+			&crtc->config->hw.pipe_mode;
 		const struct drm_framebuffer *fb =
 			crtc->base.primary->state->fb;
 		int cpp;
@@ -2383,7 +2383,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 		else
 			cpp = fb->format->cpp[0];
 
-		planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
+		planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
 					       wm_info, fifo_size, cpp,
 					       pessimal_latency_ns);
 		if (enabled == NULL)
@@ -2421,12 +2421,12 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	if (HAS_FW_BLC(dev_priv) && enabled) {
 		/* self-refresh has much higher latency */
 		static const int sr_latency_ns = 6000;
-		const struct drm_display_mode *adjusted_mode =
-			&enabled->config->hw.adjusted_mode;
+		const struct drm_display_mode *pipe_mode =
+			&enabled->config->hw.pipe_mode;
 		const struct drm_framebuffer *fb =
 			enabled->base.primary->state->fb;
-		int clock = adjusted_mode->crtc_clock;
-		int htotal = adjusted_mode->crtc_htotal;
+		int clock = pipe_mode->crtc_clock;
+		int htotal = pipe_mode->crtc_htotal;
 		int hdisplay = enabled->config->pipe_src_w;
 		int cpp;
 		int entries;
@@ -2474,7 +2474,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 	struct intel_crtc *crtc;
-	const struct drm_display_mode *adjusted_mode;
+	const struct drm_display_mode *pipe_mode;
 	u32 fwater_lo;
 	int planea_wm;
 
@@ -2482,8 +2482,8 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
 	if (crtc == NULL)
 		return;
 
-	adjusted_mode = &crtc->config->hw.adjusted_mode;
-	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
+	pipe_mode = &crtc->config->hw.pipe_mode;
+	planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
 				       &i845_wm_info,
 				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
 				       4, pessimal_latency_ns);
@@ -2573,7 +2573,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
 		return method1;
 
 	method2 = ilk_wm_method2(crtc_state->pixel_rate,
-				 crtc_state->hw.adjusted_mode.crtc_htotal,
+				 crtc_state->hw.pipe_mode.crtc_htotal,
 				 drm_rect_width(&plane_state->uapi.dst),
 				 cpp, mem_value);
 
@@ -2601,7 +2601,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
 
 	method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
 	method2 = ilk_wm_method2(crtc_state->pixel_rate,
-				 crtc_state->hw.adjusted_mode.crtc_htotal,
+				 crtc_state->hw.pipe_mode.crtc_htotal,
 				 drm_rect_width(&plane_state->uapi.dst),
 				 cpp, mem_value);
 	return min(method1, method2);
@@ -2626,7 +2626,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
 	cpp = plane_state->hw.fb->format->cpp[0];
 
 	return ilk_wm_method2(crtc_state->pixel_rate,
-			      crtc_state->hw.adjusted_mode.crtc_htotal,
+			      crtc_state->hw.pipe_mode.crtc_htotal,
 			      drm_rect_width(&plane_state->uapi.dst),
 			      cpp, mem_value);
 }
@@ -3883,7 +3883,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 	if (!crtc_state->hw.active)
 		return true;
 
-	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+	if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
 		return false;
 
 	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
@@ -4174,8 +4174,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
 	 */
 	total_slice_mask = dbuf_slice_mask;
 	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
-		const struct drm_display_mode *adjusted_mode =
-			&crtc_state->hw.adjusted_mode;
+		const struct drm_display_mode *pipe_mode =
+			&crtc_state->hw.pipe_mode;
 		enum pipe pipe = crtc->pipe;
 		int hdisplay, vdisplay;
 		u32 pipe_dbuf_slice_mask;
@@ -4205,7 +4205,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
 		if (dbuf_slice_mask != pipe_dbuf_slice_mask)
 			continue;
 
-		drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
+		drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay);
 
 		total_width_in_range += hdisplay;
 
@@ -5093,7 +5093,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
 	if (drm_WARN_ON(&dev_priv->drm, pixel_rate == 0))
 		return u32_to_fixed16(0);
 
-	crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
+	crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal;
 	linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
 
 	return linetime_us;
@@ -5282,14 +5282,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 	method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
 				 wp->cpp, latency, wp->dbuf_block_size);
 	method2 = skl_wm_method2(wp->plane_pixel_rate,
-				 crtc_state->hw.adjusted_mode.crtc_htotal,
+				 crtc_state->hw.pipe_mode.crtc_htotal,
 				 latency,
 				 wp->plane_blocks_per_line);
 
 	if (wp->y_tiled) {
 		selected_result = max_fixed16(method2, wp->y_tile_minimum);
 	} else {
-		if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
+		if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
 		     wp->dbuf_block_size < 1) &&
 		     (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
 			selected_result = method2;
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread

* [Intel-gfx] [PATCH v6 3/6] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 3/6] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split Manasi Navare
@ 2020-11-02 23:04   ` Manasi Navare
  2020-11-05 15:13     ` Ville Syrjälä
  0 siblings, 1 reply; 32+ messages in thread
From: Manasi Navare @ 2020-11-02 23:04 UTC (permalink / raw)
  To: intel-gfx

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
because of this, we need a pipe_mode for various calculations, including
for example watermarks, plane clipping, etc.

v9:
* pipe_mode in state dump nd state check (Ville)
v8:
* Add pipe_mode in readout in verify_crtc_state (Ville)
v7:
* Remove redundant comment (Ville)
* Just keep mode instead of pipe_mode (Ville)
v6:
* renaming in separate function, only pipe_mode here (Ville)
* Add description (Maarten)
v5:
* Rebase (Manasi)
v4:
* Manual rebase (Manasi)
v3:
* Change state to crtc_state, fix rebase err  (Manasi)
v2:
* Manual Rebase (Manasi)

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 51 ++++++++-----
 .../drm/i915/display/intel_display_types.h    | 11 ++-
 drivers/gpu/drm/i915/intel_pm.c               | 76 +++++++++----------
 3 files changed, 81 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e9fbcfe1649e..c045ef0ac801 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6167,18 +6167,16 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 
 static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
 {
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
+	const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
 	int width, height;
 
 	if (crtc_state->pch_pfit.enabled) {
 		width = drm_rect_width(&crtc_state->pch_pfit.dst);
 		height = drm_rect_height(&crtc_state->pch_pfit.dst);
 	} else {
-		width = adjusted_mode->crtc_hdisplay;
-		height = adjusted_mode->crtc_vdisplay;
+		width = pipe_mode->crtc_hdisplay;
+		height = pipe_mode->crtc_vdisplay;
 	}
-
 	return skl_update_scaler(crtc_state, !crtc_state->hw.active,
 				 SKL_CRTC_INDEX,
 				 &crtc_state->scaler_state.scaler_id,
@@ -8192,7 +8190,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
 
 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
 {
-	u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
+	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
 	unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
 
 	/*
@@ -8225,7 +8223,11 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
 static void intel_encoder_get_config(struct intel_encoder *encoder,
 				     struct intel_crtc_state *crtc_state)
 {
+	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
+
 	encoder->get_config(encoder, crtc_state);
+
+	*pipe_mode = crtc_state->hw.adjusted_mode;
 }
 
 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
@@ -8235,7 +8237,7 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
 	if (HAS_GMCH(dev_priv))
 		/* FIXME calculate proper pipe pixel rate for GMCH pfit */
 		crtc_state->pixel_rate =
-			crtc_state->hw.adjusted_mode.crtc_clock;
+			crtc_state->hw.pipe_mode.crtc_clock;
 	else
 		crtc_state->pixel_rate =
 			ilk_pipe_pixel_rate(crtc_state);
@@ -8245,9 +8247,11 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 				     struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+	struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
 	int clock_limit = dev_priv->max_dotclk_freq;
 
+	*pipe_mode = pipe_config->hw.adjusted_mode;
+
 	if (INTEL_GEN(dev_priv) < 4) {
 		clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
 
@@ -8256,16 +8260,16 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 		 * is > 90% of the (display) core speed.
 		 */
 		if (intel_crtc_supports_double_wide(crtc) &&
-		    adjusted_mode->crtc_clock > clock_limit) {
+		    pipe_mode->crtc_clock > clock_limit) {
 			clock_limit = dev_priv->max_dotclk_freq;
 			pipe_config->double_wide = true;
 		}
 	}
 
-	if (adjusted_mode->crtc_clock > clock_limit) {
+	if (pipe_mode->crtc_clock > clock_limit) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
-			    adjusted_mode->crtc_clock, clock_limit,
+			    pipe_mode->crtc_clock, clock_limit,
 			    yesno(pipe_config->double_wide));
 		return -EINVAL;
 	}
@@ -8308,7 +8312,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
 	 */
 	if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
-		adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
+	    pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
 		return -EINVAL;
 
 	intel_crtc_compute_pixel_rate(pipe_config);
@@ -12827,15 +12831,15 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
 
 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
 {
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
+	const struct drm_display_mode *pipe_mode =
+		&crtc_state->hw.pipe_mode;
 	int linetime_wm;
 
 	if (!crtc_state->hw.enable)
 		return 0;
 
-	linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
-					adjusted_mode->crtc_clock);
+	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
+					pipe_mode->crtc_clock);
 
 	return min(linetime_wm, 0x1ff);
 }
@@ -13322,7 +13326,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
 	drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
 	drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
+	drm_dbg_kms(&dev_priv->drm, "pipe mode:\n");
+	drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode);
 	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
+	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
 	drm_dbg_kms(&dev_priv->drm,
 		    "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
 		    pipe_config->port_clock,
@@ -13465,8 +13472,9 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
 	crtc_state->hw.enable = crtc_state->uapi.enable;
 	crtc_state->hw.active = crtc_state->uapi.active;
 	crtc_state->hw.mode = crtc_state->uapi.mode;
-	crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
+	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
 	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
+
 	intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
 }
 
@@ -13663,6 +13671,9 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
 		    "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
 		    base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
 
+	/* without bigjoiner, pipe_mode == adjusted_mode */
+	pipe_config->hw.pipe_mode = pipe_config->hw.adjusted_mode;
+
 	return 0;
 }
 
@@ -14071,6 +14082,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 	PIPE_CONF_CHECK_X(output_types);
 
+	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
+	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
+	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
+	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
 	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
 	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
 	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
@@ -18920,6 +18935,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			 */
 			crtc_state->inherited = true;
 
+			crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode;
+
 			intel_crtc_compute_pixel_rate(crtc_state);
 
 			intel_crtc_update_active_timings(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f6f0626649e0..b526afee595c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -817,15 +817,22 @@ struct intel_crtc_state {
 	 * The following members are used to verify the hardware state:
 	 * - enable
 	 * - active
-	 * - mode / adjusted_mode
+	 * - mode/adjusted_mode
 	 * - color property blobs.
 	 *
 	 * During initial hw readout, they need to be copied to uapi.
+	 *
+	 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
+	 * Use the pipe_mode for calculations like watermarks, pipe
+	 * scaler, and bandwidth.
+	 *
+	 * Use adjusted_mode for things that need to know the full
+	 * mode on the transcoder, which spans all pipes.
 	 */
 	struct {
 		bool active, enable;
 		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
-		struct drm_display_mode mode, adjusted_mode;
+		struct drm_display_mode mode, pipe_mode, adjusted_mode;
 		enum drm_scaling_filter scaling_filter;
 	} hw;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f54375b11964..9898c257d3e0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -899,12 +899,12 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc)
 
 	crtc = single_enabled_crtc(dev_priv);
 	if (crtc) {
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->hw.adjusted_mode;
+		const struct drm_display_mode *pipe_mode =
+			&crtc->config->hw.pipe_mode;
 		const struct drm_framebuffer *fb =
 			crtc->base.primary->state->fb;
 		int cpp = fb->format->cpp[0];
-		int clock = adjusted_mode->crtc_clock;
+		int clock = pipe_mode->crtc_clock;
 
 		/* Display SR */
 		wm = intel_calculate_wm(clock, &pnv_display_wm,
@@ -1135,8 +1135,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
+	const struct drm_display_mode *pipe_mode =
+		&crtc_state->hw.pipe_mode;
 	unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
 	unsigned int clock, htotal, cpp, width, wm;
 
@@ -1163,8 +1163,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
 	    level != G4X_WM_LEVEL_NORMAL)
 		cpp = max(cpp, 4u);
 
-	clock = adjusted_mode->crtc_clock;
-	htotal = adjusted_mode->crtc_htotal;
+	clock = pipe_mode->crtc_clock;
+	htotal = pipe_mode->crtc_htotal;
 
 	width = drm_rect_width(&plane_state->uapi.dst);
 
@@ -1660,8 +1660,8 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
+	const struct drm_display_mode *pipe_mode =
+		&crtc_state->hw.pipe_mode;
 	unsigned int clock, htotal, cpp, width, wm;
 
 	if (dev_priv->wm.pri_latency[level] == 0)
@@ -1671,8 +1671,8 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
 		return 0;
 
 	cpp = plane_state->hw.fb->format->cpp[0];
-	clock = adjusted_mode->crtc_clock;
-	htotal = adjusted_mode->crtc_htotal;
+	clock = pipe_mode->crtc_clock;
+	htotal = pipe_mode->crtc_htotal;
 	width = crtc_state->pipe_src_w;
 
 	if (plane->id == PLANE_CURSOR) {
@@ -2261,12 +2261,12 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
 	if (crtc) {
 		/* self-refresh has much higher latency */
 		static const int sr_latency_ns = 12000;
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->hw.adjusted_mode;
+		const struct drm_display_mode *pipe_mode =
+			&crtc->config->hw.pipe_mode;
 		const struct drm_framebuffer *fb =
 			crtc->base.primary->state->fb;
-		int clock = adjusted_mode->crtc_clock;
-		int htotal = adjusted_mode->crtc_htotal;
+		int clock = pipe_mode->crtc_clock;
+		int htotal = pipe_mode->crtc_htotal;
 		int hdisplay = crtc->config->pipe_src_w;
 		int cpp = fb->format->cpp[0];
 		int entries;
@@ -2345,8 +2345,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
 	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
 	if (intel_crtc_active(crtc)) {
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->hw.adjusted_mode;
+		const struct drm_display_mode *pipe_mode =
+			&crtc->config->hw.pipe_mode;
 		const struct drm_framebuffer *fb =
 			crtc->base.primary->state->fb;
 		int cpp;
@@ -2356,7 +2356,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 		else
 			cpp = fb->format->cpp[0];
 
-		planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
+		planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
 					       wm_info, fifo_size, cpp,
 					       pessimal_latency_ns);
 		enabled = crtc;
@@ -2372,8 +2372,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
 	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
 	if (intel_crtc_active(crtc)) {
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->hw.adjusted_mode;
+		const struct drm_display_mode *pipe_mode =
+			&crtc->config->hw.pipe_mode;
 		const struct drm_framebuffer *fb =
 			crtc->base.primary->state->fb;
 		int cpp;
@@ -2383,7 +2383,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 		else
 			cpp = fb->format->cpp[0];
 
-		planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
+		planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
 					       wm_info, fifo_size, cpp,
 					       pessimal_latency_ns);
 		if (enabled == NULL)
@@ -2421,12 +2421,12 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	if (HAS_FW_BLC(dev_priv) && enabled) {
 		/* self-refresh has much higher latency */
 		static const int sr_latency_ns = 6000;
-		const struct drm_display_mode *adjusted_mode =
-			&enabled->config->hw.adjusted_mode;
+		const struct drm_display_mode *pipe_mode =
+			&enabled->config->hw.pipe_mode;
 		const struct drm_framebuffer *fb =
 			enabled->base.primary->state->fb;
-		int clock = adjusted_mode->crtc_clock;
-		int htotal = adjusted_mode->crtc_htotal;
+		int clock = pipe_mode->crtc_clock;
+		int htotal = pipe_mode->crtc_htotal;
 		int hdisplay = enabled->config->pipe_src_w;
 		int cpp;
 		int entries;
@@ -2474,7 +2474,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 	struct intel_crtc *crtc;
-	const struct drm_display_mode *adjusted_mode;
+	const struct drm_display_mode *pipe_mode;
 	u32 fwater_lo;
 	int planea_wm;
 
@@ -2482,8 +2482,8 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
 	if (crtc == NULL)
 		return;
 
-	adjusted_mode = &crtc->config->hw.adjusted_mode;
-	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
+	pipe_mode = &crtc->config->hw.pipe_mode;
+	planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
 				       &i845_wm_info,
 				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
 				       4, pessimal_latency_ns);
@@ -2573,7 +2573,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
 		return method1;
 
 	method2 = ilk_wm_method2(crtc_state->pixel_rate,
-				 crtc_state->hw.adjusted_mode.crtc_htotal,
+				 crtc_state->hw.pipe_mode.crtc_htotal,
 				 drm_rect_width(&plane_state->uapi.dst),
 				 cpp, mem_value);
 
@@ -2601,7 +2601,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
 
 	method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
 	method2 = ilk_wm_method2(crtc_state->pixel_rate,
-				 crtc_state->hw.adjusted_mode.crtc_htotal,
+				 crtc_state->hw.pipe_mode.crtc_htotal,
 				 drm_rect_width(&plane_state->uapi.dst),
 				 cpp, mem_value);
 	return min(method1, method2);
@@ -2626,7 +2626,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
 	cpp = plane_state->hw.fb->format->cpp[0];
 
 	return ilk_wm_method2(crtc_state->pixel_rate,
-			      crtc_state->hw.adjusted_mode.crtc_htotal,
+			      crtc_state->hw.pipe_mode.crtc_htotal,
 			      drm_rect_width(&plane_state->uapi.dst),
 			      cpp, mem_value);
 }
@@ -3883,7 +3883,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 	if (!crtc_state->hw.active)
 		return true;
 
-	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+	if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
 		return false;
 
 	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
@@ -4174,8 +4174,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
 	 */
 	total_slice_mask = dbuf_slice_mask;
 	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
-		const struct drm_display_mode *adjusted_mode =
-			&crtc_state->hw.adjusted_mode;
+		const struct drm_display_mode *pipe_mode =
+			&crtc_state->hw.pipe_mode;
 		enum pipe pipe = crtc->pipe;
 		int hdisplay, vdisplay;
 		u32 pipe_dbuf_slice_mask;
@@ -4205,7 +4205,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
 		if (dbuf_slice_mask != pipe_dbuf_slice_mask)
 			continue;
 
-		drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
+		drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay);
 
 		total_width_in_range += hdisplay;
 
@@ -5093,7 +5093,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
 	if (drm_WARN_ON(&dev_priv->drm, pixel_rate == 0))
 		return u32_to_fixed16(0);
 
-	crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
+	crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal;
 	linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
 
 	return linetime_us;
@@ -5282,14 +5282,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 	method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
 				 wp->cpp, latency, wp->dbuf_block_size);
 	method2 = skl_wm_method2(wp->plane_pixel_rate,
-				 crtc_state->hw.adjusted_mode.crtc_htotal,
+				 crtc_state->hw.pipe_mode.crtc_htotal,
 				 latency,
 				 wp->plane_blocks_per_line);
 
 	if (wp->y_tiled) {
 		selected_result = max_fixed16(method2, wp->y_tile_minimum);
 	} else {
-		if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
+		if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
 		     wp->dbuf_block_size < 1) &&
 		     (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
 			selected_result = method2;
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread

* Re: [Intel-gfx] [PATCH v6 3/6] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
  2020-11-02 23:04   ` [Intel-gfx] [PATCH v6 " Manasi Navare
@ 2020-11-05 15:13     ` Ville Syrjälä
  2020-11-05 16:03       ` Navare, Manasi
  0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2020-11-05 15:13 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx

On Mon, Nov 02, 2020 at 03:04:00PM -0800, Manasi Navare wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> 
> With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
> because of this, we need a pipe_mode for various calculations, including
> for example watermarks, plane clipping, etc.
> 
> v9:
> * pipe_mode in state dump nd state check (Ville)
> v8:
> * Add pipe_mode in readout in verify_crtc_state (Ville)
> v7:
> * Remove redundant comment (Ville)
> * Just keep mode instead of pipe_mode (Ville)
> v6:
> * renaming in separate function, only pipe_mode here (Ville)
> * Add description (Maarten)
> v5:
> * Rebase (Manasi)
> v4:
> * Manual rebase (Manasi)
> v3:
> * Change state to crtc_state, fix rebase err  (Manasi)
> v2:
> * Manual Rebase (Manasi)
> 
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Animesh Manna <animesh.manna@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 51 ++++++++-----
>  .../drm/i915/display/intel_display_types.h    | 11 ++-
>  drivers/gpu/drm/i915/intel_pm.c               | 76 +++++++++----------
>  3 files changed, 81 insertions(+), 57 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e9fbcfe1649e..c045ef0ac801 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6167,18 +6167,16 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>  
>  static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
>  {
> -	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->hw.adjusted_mode;
> +	const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
>  	int width, height;
>  
>  	if (crtc_state->pch_pfit.enabled) {
>  		width = drm_rect_width(&crtc_state->pch_pfit.dst);
>  		height = drm_rect_height(&crtc_state->pch_pfit.dst);
>  	} else {
> -		width = adjusted_mode->crtc_hdisplay;
> -		height = adjusted_mode->crtc_vdisplay;
> +		width = pipe_mode->crtc_hdisplay;
> +		height = pipe_mode->crtc_vdisplay;
>  	}
> -
>  	return skl_update_scaler(crtc_state, !crtc_state->hw.active,
>  				 SKL_CRTC_INDEX,
>  				 &crtc_state->scaler_state.scaler_id,
> @@ -8192,7 +8190,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
>  
>  static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
>  {
> -	u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
> +	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
>  	unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
>  
>  	/*
> @@ -8225,7 +8223,11 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
>  static void intel_encoder_get_config(struct intel_encoder *encoder,
>  				     struct intel_crtc_state *crtc_state)
>  {
> +	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> +
>  	encoder->get_config(encoder, crtc_state);
> +
> +	*pipe_mode = crtc_state->hw.adjusted_mode;
>  }
>  
>  static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> @@ -8235,7 +8237,7 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
>  	if (HAS_GMCH(dev_priv))
>  		/* FIXME calculate proper pipe pixel rate for GMCH pfit */
>  		crtc_state->pixel_rate =
> -			crtc_state->hw.adjusted_mode.crtc_clock;
> +			crtc_state->hw.pipe_mode.crtc_clock;
>  	else
>  		crtc_state->pixel_rate =
>  			ilk_pipe_pixel_rate(crtc_state);
> @@ -8245,9 +8247,11 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>  				     struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> +	struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
>  	int clock_limit = dev_priv->max_dotclk_freq;
>  
> +	*pipe_mode = pipe_config->hw.adjusted_mode;

That will now overwrite whatever the encoder computed in
.compute_config(). Wasn't that where we wanted to do it for actual
bigjoiner, or was that going to be somewhere else?

An alternative would be to do this before .compute_config() +
also in intel_fixed_panel_mode() for eDP/etc.

> +
>  	if (INTEL_GEN(dev_priv) < 4) {
>  		clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
>  
> @@ -8256,16 +8260,16 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>  		 * is > 90% of the (display) core speed.
>  		 */
>  		if (intel_crtc_supports_double_wide(crtc) &&
> -		    adjusted_mode->crtc_clock > clock_limit) {
> +		    pipe_mode->crtc_clock > clock_limit) {
>  			clock_limit = dev_priv->max_dotclk_freq;
>  			pipe_config->double_wide = true;
>  		}
>  	}
>  
> -	if (adjusted_mode->crtc_clock > clock_limit) {
> +	if (pipe_mode->crtc_clock > clock_limit) {
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
> -			    adjusted_mode->crtc_clock, clock_limit,
> +			    pipe_mode->crtc_clock, clock_limit,
>  			    yesno(pipe_config->double_wide));
>  		return -EINVAL;
>  	}
> @@ -8308,7 +8312,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>  	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
>  	 */
>  	if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
> -		adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
> +	    pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
>  		return -EINVAL;
>  
>  	intel_crtc_compute_pixel_rate(pipe_config);
> @@ -12827,15 +12831,15 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
>  
>  static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
>  {
> -	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->hw.adjusted_mode;
> +	const struct drm_display_mode *pipe_mode =
> +		&crtc_state->hw.pipe_mode;
>  	int linetime_wm;
>  
>  	if (!crtc_state->hw.enable)
>  		return 0;
>  
> -	linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
> -					adjusted_mode->crtc_clock);
> +	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
> +					pipe_mode->crtc_clock);
>  
>  	return min(linetime_wm, 0x1ff);
>  }
> @@ -13322,7 +13326,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>  	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
>  	drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
>  	drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
> +	drm_dbg_kms(&dev_priv->drm, "pipe mode:\n");
> +	drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode);
>  	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
> +	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
>  	drm_dbg_kms(&dev_priv->drm,
>  		    "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
>  		    pipe_config->port_clock,
> @@ -13465,8 +13472,9 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
>  	crtc_state->hw.enable = crtc_state->uapi.enable;
>  	crtc_state->hw.active = crtc_state->uapi.active;
>  	crtc_state->hw.mode = crtc_state->uapi.mode;
> -	crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
> +	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
>  	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
> +
>  	intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
>  }
>  
> @@ -13663,6 +13671,9 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
>  		    "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
>  		    base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
>  
> +	/* without bigjoiner, pipe_mode == adjusted_mode */
> +	pipe_config->hw.pipe_mode = pipe_config->hw.adjusted_mode;
> +
>  	return 0;
>  }
>  
> @@ -14071,6 +14082,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  
>  	PIPE_CONF_CHECK_X(output_types);
>  
> +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
>  	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
>  	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
>  	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> @@ -18920,6 +18935,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  			 */
>  			crtc_state->inherited = true;
>  
> +			crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode;
> +

Isn't this redundant now?

>  			intel_crtc_compute_pixel_rate(crtc_state);
>  
>  			intel_crtc_update_active_timings(crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f6f0626649e0..b526afee595c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -817,15 +817,22 @@ struct intel_crtc_state {
>  	 * The following members are used to verify the hardware state:
>  	 * - enable
>  	 * - active
> -	 * - mode / adjusted_mode
> +	 * - mode/adjusted_mode
>  	 * - color property blobs.
>  	 *
>  	 * During initial hw readout, they need to be copied to uapi.
> +	 *
> +	 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
> +	 * Use the pipe_mode for calculations like watermarks, pipe
> +	 * scaler, and bandwidth.
> +	 *
> +	 * Use adjusted_mode for things that need to know the full
> +	 * mode on the transcoder, which spans all pipes.
>  	 */
>  	struct {
>  		bool active, enable;
>  		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
> -		struct drm_display_mode mode, adjusted_mode;
> +		struct drm_display_mode mode, pipe_mode, adjusted_mode;
>  		enum drm_scaling_filter scaling_filter;
>  	} hw;
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f54375b11964..9898c257d3e0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -899,12 +899,12 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc)
>  
>  	crtc = single_enabled_crtc(dev_priv);
>  	if (crtc) {
> -		const struct drm_display_mode *adjusted_mode =
> -			&crtc->config->hw.adjusted_mode;
> +		const struct drm_display_mode *pipe_mode =
> +			&crtc->config->hw.pipe_mode;
>  		const struct drm_framebuffer *fb =
>  			crtc->base.primary->state->fb;
>  		int cpp = fb->format->cpp[0];
> -		int clock = adjusted_mode->crtc_clock;
> +		int clock = pipe_mode->crtc_clock;
>  
>  		/* Display SR */
>  		wm = intel_calculate_wm(clock, &pnv_display_wm,
> @@ -1135,8 +1135,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
>  {
>  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> -	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->hw.adjusted_mode;
> +	const struct drm_display_mode *pipe_mode =
> +		&crtc_state->hw.pipe_mode;
>  	unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
>  	unsigned int clock, htotal, cpp, width, wm;
>  
> @@ -1163,8 +1163,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
>  	    level != G4X_WM_LEVEL_NORMAL)
>  		cpp = max(cpp, 4u);
>  
> -	clock = adjusted_mode->crtc_clock;
> -	htotal = adjusted_mode->crtc_htotal;
> +	clock = pipe_mode->crtc_clock;
> +	htotal = pipe_mode->crtc_htotal;
>  
>  	width = drm_rect_width(&plane_state->uapi.dst);
>  
> @@ -1660,8 +1660,8 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
>  {
>  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> -	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->hw.adjusted_mode;
> +	const struct drm_display_mode *pipe_mode =
> +		&crtc_state->hw.pipe_mode;
>  	unsigned int clock, htotal, cpp, width, wm;
>  
>  	if (dev_priv->wm.pri_latency[level] == 0)
> @@ -1671,8 +1671,8 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
>  		return 0;
>  
>  	cpp = plane_state->hw.fb->format->cpp[0];
> -	clock = adjusted_mode->crtc_clock;
> -	htotal = adjusted_mode->crtc_htotal;
> +	clock = pipe_mode->crtc_clock;
> +	htotal = pipe_mode->crtc_htotal;
>  	width = crtc_state->pipe_src_w;
>  
>  	if (plane->id == PLANE_CURSOR) {
> @@ -2261,12 +2261,12 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
>  	if (crtc) {
>  		/* self-refresh has much higher latency */
>  		static const int sr_latency_ns = 12000;
> -		const struct drm_display_mode *adjusted_mode =
> -			&crtc->config->hw.adjusted_mode;
> +		const struct drm_display_mode *pipe_mode =
> +			&crtc->config->hw.pipe_mode;
>  		const struct drm_framebuffer *fb =
>  			crtc->base.primary->state->fb;
> -		int clock = adjusted_mode->crtc_clock;
> -		int htotal = adjusted_mode->crtc_htotal;
> +		int clock = pipe_mode->crtc_clock;
> +		int htotal = pipe_mode->crtc_htotal;
>  		int hdisplay = crtc->config->pipe_src_w;
>  		int cpp = fb->format->cpp[0];
>  		int entries;
> @@ -2345,8 +2345,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
>  	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
>  	if (intel_crtc_active(crtc)) {
> -		const struct drm_display_mode *adjusted_mode =
> -			&crtc->config->hw.adjusted_mode;
> +		const struct drm_display_mode *pipe_mode =
> +			&crtc->config->hw.pipe_mode;
>  		const struct drm_framebuffer *fb =
>  			crtc->base.primary->state->fb;
>  		int cpp;
> @@ -2356,7 +2356,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  		else
>  			cpp = fb->format->cpp[0];
>  
> -		planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> +		planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
>  					       wm_info, fifo_size, cpp,
>  					       pessimal_latency_ns);
>  		enabled = crtc;
> @@ -2372,8 +2372,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
>  	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
>  	if (intel_crtc_active(crtc)) {
> -		const struct drm_display_mode *adjusted_mode =
> -			&crtc->config->hw.adjusted_mode;
> +		const struct drm_display_mode *pipe_mode =
> +			&crtc->config->hw.pipe_mode;
>  		const struct drm_framebuffer *fb =
>  			crtc->base.primary->state->fb;
>  		int cpp;
> @@ -2383,7 +2383,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  		else
>  			cpp = fb->format->cpp[0];
>  
> -		planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> +		planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
>  					       wm_info, fifo_size, cpp,
>  					       pessimal_latency_ns);
>  		if (enabled == NULL)
> @@ -2421,12 +2421,12 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  	if (HAS_FW_BLC(dev_priv) && enabled) {
>  		/* self-refresh has much higher latency */
>  		static const int sr_latency_ns = 6000;
> -		const struct drm_display_mode *adjusted_mode =
> -			&enabled->config->hw.adjusted_mode;
> +		const struct drm_display_mode *pipe_mode =
> +			&enabled->config->hw.pipe_mode;
>  		const struct drm_framebuffer *fb =
>  			enabled->base.primary->state->fb;
> -		int clock = adjusted_mode->crtc_clock;
> -		int htotal = adjusted_mode->crtc_htotal;
> +		int clock = pipe_mode->crtc_clock;
> +		int htotal = pipe_mode->crtc_htotal;
>  		int hdisplay = enabled->config->pipe_src_w;
>  		int cpp;
>  		int entries;
> @@ -2474,7 +2474,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
>  	struct intel_crtc *crtc;
> -	const struct drm_display_mode *adjusted_mode;
> +	const struct drm_display_mode *pipe_mode;
>  	u32 fwater_lo;
>  	int planea_wm;
>  
> @@ -2482,8 +2482,8 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
>  	if (crtc == NULL)
>  		return;
>  
> -	adjusted_mode = &crtc->config->hw.adjusted_mode;
> -	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> +	pipe_mode = &crtc->config->hw.pipe_mode;
> +	planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
>  				       &i845_wm_info,
>  				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
>  				       4, pessimal_latency_ns);
> @@ -2573,7 +2573,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
>  		return method1;
>  
>  	method2 = ilk_wm_method2(crtc_state->pixel_rate,
> -				 crtc_state->hw.adjusted_mode.crtc_htotal,
> +				 crtc_state->hw.pipe_mode.crtc_htotal,
>  				 drm_rect_width(&plane_state->uapi.dst),
>  				 cpp, mem_value);
>  
> @@ -2601,7 +2601,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
>  
>  	method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
>  	method2 = ilk_wm_method2(crtc_state->pixel_rate,
> -				 crtc_state->hw.adjusted_mode.crtc_htotal,
> +				 crtc_state->hw.pipe_mode.crtc_htotal,
>  				 drm_rect_width(&plane_state->uapi.dst),
>  				 cpp, mem_value);
>  	return min(method1, method2);
> @@ -2626,7 +2626,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
>  	cpp = plane_state->hw.fb->format->cpp[0];
>  
>  	return ilk_wm_method2(crtc_state->pixel_rate,
> -			      crtc_state->hw.adjusted_mode.crtc_htotal,
> +			      crtc_state->hw.pipe_mode.crtc_htotal,
>  			      drm_rect_width(&plane_state->uapi.dst),
>  			      cpp, mem_value);
>  }
> @@ -3883,7 +3883,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
>  	if (!crtc_state->hw.active)
>  		return true;
>  
> -	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> +	if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
>  		return false;
>  
>  	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> @@ -4174,8 +4174,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
>  	 */
>  	total_slice_mask = dbuf_slice_mask;
>  	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> -		const struct drm_display_mode *adjusted_mode =
> -			&crtc_state->hw.adjusted_mode;
> +		const struct drm_display_mode *pipe_mode =
> +			&crtc_state->hw.pipe_mode;
>  		enum pipe pipe = crtc->pipe;
>  		int hdisplay, vdisplay;
>  		u32 pipe_dbuf_slice_mask;
> @@ -4205,7 +4205,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
>  		if (dbuf_slice_mask != pipe_dbuf_slice_mask)
>  			continue;
>  
> -		drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
> +		drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay);
>  
>  		total_width_in_range += hdisplay;
>  
> @@ -5093,7 +5093,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
>  	if (drm_WARN_ON(&dev_priv->drm, pixel_rate == 0))
>  		return u32_to_fixed16(0);
>  
> -	crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
> +	crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal;
>  	linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
>  
>  	return linetime_us;
> @@ -5282,14 +5282,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>  	method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
>  				 wp->cpp, latency, wp->dbuf_block_size);
>  	method2 = skl_wm_method2(wp->plane_pixel_rate,
> -				 crtc_state->hw.adjusted_mode.crtc_htotal,
> +				 crtc_state->hw.pipe_mode.crtc_htotal,
>  				 latency,
>  				 wp->plane_blocks_per_line);
>  
>  	if (wp->y_tiled) {
>  		selected_result = max_fixed16(method2, wp->y_tile_minimum);
>  	} else {
> -		if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
> +		if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
>  		     wp->dbuf_block_size < 1) &&
>  		     (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
>  			selected_result = method2;
> -- 
> 2.19.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [Intel-gfx] [PATCH v6 3/6] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
  2020-11-05 15:13     ` Ville Syrjälä
@ 2020-11-05 16:03       ` Navare, Manasi
  2020-11-05 16:15         ` Ville Syrjälä
  0 siblings, 1 reply; 32+ messages in thread
From: Navare, Manasi @ 2020-11-05 16:03 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Thu, Nov 05, 2020 at 05:13:04PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 02, 2020 at 03:04:00PM -0800, Manasi Navare wrote:
> > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > 
> > With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
> > because of this, we need a pipe_mode for various calculations, including
> > for example watermarks, plane clipping, etc.
> > 
> > v9:
> > * pipe_mode in state dump nd state check (Ville)
> > v8:
> > * Add pipe_mode in readout in verify_crtc_state (Ville)
> > v7:
> > * Remove redundant comment (Ville)
> > * Just keep mode instead of pipe_mode (Ville)
> > v6:
> > * renaming in separate function, only pipe_mode here (Ville)
> > * Add description (Maarten)
> > v5:
> > * Rebase (Manasi)
> > v4:
> > * Manual rebase (Manasi)
> > v3:
> > * Change state to crtc_state, fix rebase err  (Manasi)
> > v2:
> > * Manual Rebase (Manasi)
> > 
> > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Reviewed-by: Animesh Manna <animesh.manna@intel.com>
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  | 51 ++++++++-----
> >  .../drm/i915/display/intel_display_types.h    | 11 ++-
> >  drivers/gpu/drm/i915/intel_pm.c               | 76 +++++++++----------
> >  3 files changed, 81 insertions(+), 57 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index e9fbcfe1649e..c045ef0ac801 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6167,18 +6167,16 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> >  
> >  static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
> >  {
> > -	const struct drm_display_mode *adjusted_mode =
> > -		&crtc_state->hw.adjusted_mode;
> > +	const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> >  	int width, height;
> >  
> >  	if (crtc_state->pch_pfit.enabled) {
> >  		width = drm_rect_width(&crtc_state->pch_pfit.dst);
> >  		height = drm_rect_height(&crtc_state->pch_pfit.dst);
> >  	} else {
> > -		width = adjusted_mode->crtc_hdisplay;
> > -		height = adjusted_mode->crtc_vdisplay;
> > +		width = pipe_mode->crtc_hdisplay;
> > +		height = pipe_mode->crtc_vdisplay;
> >  	}
> > -
> >  	return skl_update_scaler(crtc_state, !crtc_state->hw.active,
> >  				 SKL_CRTC_INDEX,
> >  				 &crtc_state->scaler_state.scaler_id,
> > @@ -8192,7 +8190,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
> >  
> >  static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
> >  {
> > -	u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
> > +	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
> >  	unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
> >  
> >  	/*
> > @@ -8225,7 +8223,11 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
> >  static void intel_encoder_get_config(struct intel_encoder *encoder,
> >  				     struct intel_crtc_state *crtc_state)
> >  {
> > +	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> > +
> >  	encoder->get_config(encoder, crtc_state);
> > +
> > +	*pipe_mode = crtc_state->hw.adjusted_mode;
> >  }
> >  
> >  static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> > @@ -8235,7 +8237,7 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> >  	if (HAS_GMCH(dev_priv))
> >  		/* FIXME calculate proper pipe pixel rate for GMCH pfit */
> >  		crtc_state->pixel_rate =
> > -			crtc_state->hw.adjusted_mode.crtc_clock;
> > +			crtc_state->hw.pipe_mode.crtc_clock;
> >  	else
> >  		crtc_state->pixel_rate =
> >  			ilk_pipe_pixel_rate(crtc_state);
> > @@ -8245,9 +8247,11 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> >  				     struct intel_crtc_state *pipe_config)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > -	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> > +	struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
> >  	int clock_limit = dev_priv->max_dotclk_freq;
> >  
> > +	*pipe_mode = pipe_config->hw.adjusted_mode;
> 
> That will now overwrite whatever the encoder computed in
> .compute_config(). Wasn't that where we wanted to do it for actual
> bigjoiner, or was that going to be somewhere else?

We compute the pipe mode for bigjoiner in this function:

static int intel_crtc_compute_config(struct intel_crtc *crtc,
                                     struct intel_crtc_state *pipe_config)
{
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
        int clock_limit = dev_priv->max_dotclk_freq;

        *pipe_mode = pipe_config->hw.adjusted_mode;

        /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
        if (pipe_config->bigjoiner) {
                pipe_mode->crtc_clock /= 2;
                pipe_mode->crtc_hdisplay /= 2;
                pipe_mode->crtc_hblank_start /= 2;
                pipe_mode->crtc_hblank_end /= 2;
                pipe_mode->crtc_hsync_start /= 2;
                pipe_mode->crtc_hsync_end /= 2;
                pipe_mode->crtc_htotal /= 2;
                pipe_mode->crtc_hskew /= 2;
                pipe_config->pipe_src_w /= 2;
        }

So thats why in this patch we just add *pipe_mode = pipe_config->hw.adjusted_mode; the actual big joiner stuff gets added
in the core big joiner patch : https://patchwork.freedesktop.org/patch/398457/?series=83379&rev=1


> 
> An alternative would be to do this before .compute_config() +
> also in intel_fixed_panel_mode() for eDP/etc.
> 
> > +
> >  	if (INTEL_GEN(dev_priv) < 4) {
> >  		clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
> >  
> > @@ -8256,16 +8260,16 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> >  		 * is > 90% of the (display) core speed.
> >  		 */
> >  		if (intel_crtc_supports_double_wide(crtc) &&
> > -		    adjusted_mode->crtc_clock > clock_limit) {
> > +		    pipe_mode->crtc_clock > clock_limit) {
> >  			clock_limit = dev_priv->max_dotclk_freq;
> >  			pipe_config->double_wide = true;
> >  		}
> >  	}
> >  
> > -	if (adjusted_mode->crtc_clock > clock_limit) {
> > +	if (pipe_mode->crtc_clock > clock_limit) {
> >  		drm_dbg_kms(&dev_priv->drm,
> >  			    "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
> > -			    adjusted_mode->crtc_clock, clock_limit,
> > +			    pipe_mode->crtc_clock, clock_limit,
> >  			    yesno(pipe_config->double_wide));
> >  		return -EINVAL;
> >  	}
> > @@ -8308,7 +8312,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> >  	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
> >  	 */
> >  	if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
> > -		adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
> > +	    pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
> >  		return -EINVAL;
> >  
> >  	intel_crtc_compute_pixel_rate(pipe_config);
> > @@ -12827,15 +12831,15 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
> >  
> >  static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
> >  {
> > -	const struct drm_display_mode *adjusted_mode =
> > -		&crtc_state->hw.adjusted_mode;
> > +	const struct drm_display_mode *pipe_mode =
> > +		&crtc_state->hw.pipe_mode;
> >  	int linetime_wm;
> >  
> >  	if (!crtc_state->hw.enable)
> >  		return 0;
> >  
> > -	linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
> > -					adjusted_mode->crtc_clock);
> > +	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
> > +					pipe_mode->crtc_clock);
> >  
> >  	return min(linetime_wm, 0x1ff);
> >  }
> > @@ -13322,7 +13326,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
> >  	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> >  	drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
> >  	drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
> > +	drm_dbg_kms(&dev_priv->drm, "pipe mode:\n");
> > +	drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode);
> >  	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
> > +	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
> >  	drm_dbg_kms(&dev_priv->drm,
> >  		    "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
> >  		    pipe_config->port_clock,
> > @@ -13465,8 +13472,9 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
> >  	crtc_state->hw.enable = crtc_state->uapi.enable;
> >  	crtc_state->hw.active = crtc_state->uapi.active;
> >  	crtc_state->hw.mode = crtc_state->uapi.mode;
> > -	crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
> > +	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
> >  	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
> > +
> >  	intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
> >  }
> >  
> > @@ -13663,6 +13671,9 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> >  		    "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
> >  		    base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
> >  
> > +	/* without bigjoiner, pipe_mode == adjusted_mode */
> > +	pipe_config->hw.pipe_mode = pipe_config->hw.adjusted_mode;
> > +
> >  	return 0;
> >  }
> >  
> > @@ -14071,6 +14082,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> >  
> >  	PIPE_CONF_CHECK_X(output_types);
> >  
> > +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> >  	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> >  	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> >  	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> > @@ -18920,6 +18935,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> >  			 */
> >  			crtc_state->inherited = true;
> >  
> > +			crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode;
> > +
> 
> Isn't this redundant now?

Why is this redundant? I think we need this because then intel_crtc_compute_pixel_rate() call actually uses pipe_mode
for getting pixel rate.

Manasi


> 
> >  			intel_crtc_compute_pixel_rate(crtc_state);
> >  
> >  			intel_crtc_update_active_timings(crtc_state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index f6f0626649e0..b526afee595c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -817,15 +817,22 @@ struct intel_crtc_state {
> >  	 * The following members are used to verify the hardware state:
> >  	 * - enable
> >  	 * - active
> > -	 * - mode / adjusted_mode
> > +	 * - mode/adjusted_mode
> >  	 * - color property blobs.
> >  	 *
> >  	 * During initial hw readout, they need to be copied to uapi.
> > +	 *
> > +	 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
> > +	 * Use the pipe_mode for calculations like watermarks, pipe
> > +	 * scaler, and bandwidth.
> > +	 *
> > +	 * Use adjusted_mode for things that need to know the full
> > +	 * mode on the transcoder, which spans all pipes.
> >  	 */
> >  	struct {
> >  		bool active, enable;
> >  		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
> > -		struct drm_display_mode mode, adjusted_mode;
> > +		struct drm_display_mode mode, pipe_mode, adjusted_mode;
> >  		enum drm_scaling_filter scaling_filter;
> >  	} hw;
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index f54375b11964..9898c257d3e0 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -899,12 +899,12 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc)
> >  
> >  	crtc = single_enabled_crtc(dev_priv);
> >  	if (crtc) {
> > -		const struct drm_display_mode *adjusted_mode =
> > -			&crtc->config->hw.adjusted_mode;
> > +		const struct drm_display_mode *pipe_mode =
> > +			&crtc->config->hw.pipe_mode;
> >  		const struct drm_framebuffer *fb =
> >  			crtc->base.primary->state->fb;
> >  		int cpp = fb->format->cpp[0];
> > -		int clock = adjusted_mode->crtc_clock;
> > +		int clock = pipe_mode->crtc_clock;
> >  
> >  		/* Display SR */
> >  		wm = intel_calculate_wm(clock, &pnv_display_wm,
> > @@ -1135,8 +1135,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> >  {
> >  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > -	const struct drm_display_mode *adjusted_mode =
> > -		&crtc_state->hw.adjusted_mode;
> > +	const struct drm_display_mode *pipe_mode =
> > +		&crtc_state->hw.pipe_mode;
> >  	unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
> >  	unsigned int clock, htotal, cpp, width, wm;
> >  
> > @@ -1163,8 +1163,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> >  	    level != G4X_WM_LEVEL_NORMAL)
> >  		cpp = max(cpp, 4u);
> >  
> > -	clock = adjusted_mode->crtc_clock;
> > -	htotal = adjusted_mode->crtc_htotal;
> > +	clock = pipe_mode->crtc_clock;
> > +	htotal = pipe_mode->crtc_htotal;
> >  
> >  	width = drm_rect_width(&plane_state->uapi.dst);
> >  
> > @@ -1660,8 +1660,8 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
> >  {
> >  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > -	const struct drm_display_mode *adjusted_mode =
> > -		&crtc_state->hw.adjusted_mode;
> > +	const struct drm_display_mode *pipe_mode =
> > +		&crtc_state->hw.pipe_mode;
> >  	unsigned int clock, htotal, cpp, width, wm;
> >  
> >  	if (dev_priv->wm.pri_latency[level] == 0)
> > @@ -1671,8 +1671,8 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
> >  		return 0;
> >  
> >  	cpp = plane_state->hw.fb->format->cpp[0];
> > -	clock = adjusted_mode->crtc_clock;
> > -	htotal = adjusted_mode->crtc_htotal;
> > +	clock = pipe_mode->crtc_clock;
> > +	htotal = pipe_mode->crtc_htotal;
> >  	width = crtc_state->pipe_src_w;
> >  
> >  	if (plane->id == PLANE_CURSOR) {
> > @@ -2261,12 +2261,12 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
> >  	if (crtc) {
> >  		/* self-refresh has much higher latency */
> >  		static const int sr_latency_ns = 12000;
> > -		const struct drm_display_mode *adjusted_mode =
> > -			&crtc->config->hw.adjusted_mode;
> > +		const struct drm_display_mode *pipe_mode =
> > +			&crtc->config->hw.pipe_mode;
> >  		const struct drm_framebuffer *fb =
> >  			crtc->base.primary->state->fb;
> > -		int clock = adjusted_mode->crtc_clock;
> > -		int htotal = adjusted_mode->crtc_htotal;
> > +		int clock = pipe_mode->crtc_clock;
> > +		int htotal = pipe_mode->crtc_htotal;
> >  		int hdisplay = crtc->config->pipe_src_w;
> >  		int cpp = fb->format->cpp[0];
> >  		int entries;
> > @@ -2345,8 +2345,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> >  	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
> >  	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
> >  	if (intel_crtc_active(crtc)) {
> > -		const struct drm_display_mode *adjusted_mode =
> > -			&crtc->config->hw.adjusted_mode;
> > +		const struct drm_display_mode *pipe_mode =
> > +			&crtc->config->hw.pipe_mode;
> >  		const struct drm_framebuffer *fb =
> >  			crtc->base.primary->state->fb;
> >  		int cpp;
> > @@ -2356,7 +2356,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> >  		else
> >  			cpp = fb->format->cpp[0];
> >  
> > -		planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> > +		planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
> >  					       wm_info, fifo_size, cpp,
> >  					       pessimal_latency_ns);
> >  		enabled = crtc;
> > @@ -2372,8 +2372,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> >  	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
> >  	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
> >  	if (intel_crtc_active(crtc)) {
> > -		const struct drm_display_mode *adjusted_mode =
> > -			&crtc->config->hw.adjusted_mode;
> > +		const struct drm_display_mode *pipe_mode =
> > +			&crtc->config->hw.pipe_mode;
> >  		const struct drm_framebuffer *fb =
> >  			crtc->base.primary->state->fb;
> >  		int cpp;
> > @@ -2383,7 +2383,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> >  		else
> >  			cpp = fb->format->cpp[0];
> >  
> > -		planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> > +		planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
> >  					       wm_info, fifo_size, cpp,
> >  					       pessimal_latency_ns);
> >  		if (enabled == NULL)
> > @@ -2421,12 +2421,12 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> >  	if (HAS_FW_BLC(dev_priv) && enabled) {
> >  		/* self-refresh has much higher latency */
> >  		static const int sr_latency_ns = 6000;
> > -		const struct drm_display_mode *adjusted_mode =
> > -			&enabled->config->hw.adjusted_mode;
> > +		const struct drm_display_mode *pipe_mode =
> > +			&enabled->config->hw.pipe_mode;
> >  		const struct drm_framebuffer *fb =
> >  			enabled->base.primary->state->fb;
> > -		int clock = adjusted_mode->crtc_clock;
> > -		int htotal = adjusted_mode->crtc_htotal;
> > +		int clock = pipe_mode->crtc_clock;
> > +		int htotal = pipe_mode->crtc_htotal;
> >  		int hdisplay = enabled->config->pipe_src_w;
> >  		int cpp;
> >  		int entries;
> > @@ -2474,7 +2474,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
> >  	struct intel_crtc *crtc;
> > -	const struct drm_display_mode *adjusted_mode;
> > +	const struct drm_display_mode *pipe_mode;
> >  	u32 fwater_lo;
> >  	int planea_wm;
> >  
> > @@ -2482,8 +2482,8 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
> >  	if (crtc == NULL)
> >  		return;
> >  
> > -	adjusted_mode = &crtc->config->hw.adjusted_mode;
> > -	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> > +	pipe_mode = &crtc->config->hw.pipe_mode;
> > +	planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
> >  				       &i845_wm_info,
> >  				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
> >  				       4, pessimal_latency_ns);
> > @@ -2573,7 +2573,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
> >  		return method1;
> >  
> >  	method2 = ilk_wm_method2(crtc_state->pixel_rate,
> > -				 crtc_state->hw.adjusted_mode.crtc_htotal,
> > +				 crtc_state->hw.pipe_mode.crtc_htotal,
> >  				 drm_rect_width(&plane_state->uapi.dst),
> >  				 cpp, mem_value);
> >  
> > @@ -2601,7 +2601,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
> >  
> >  	method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
> >  	method2 = ilk_wm_method2(crtc_state->pixel_rate,
> > -				 crtc_state->hw.adjusted_mode.crtc_htotal,
> > +				 crtc_state->hw.pipe_mode.crtc_htotal,
> >  				 drm_rect_width(&plane_state->uapi.dst),
> >  				 cpp, mem_value);
> >  	return min(method1, method2);
> > @@ -2626,7 +2626,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
> >  	cpp = plane_state->hw.fb->format->cpp[0];
> >  
> >  	return ilk_wm_method2(crtc_state->pixel_rate,
> > -			      crtc_state->hw.adjusted_mode.crtc_htotal,
> > +			      crtc_state->hw.pipe_mode.crtc_htotal,
> >  			      drm_rect_width(&plane_state->uapi.dst),
> >  			      cpp, mem_value);
> >  }
> > @@ -3883,7 +3883,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> >  	if (!crtc_state->hw.active)
> >  		return true;
> >  
> > -	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > +	if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
> >  		return false;
> >  
> >  	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> > @@ -4174,8 +4174,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> >  	 */
> >  	total_slice_mask = dbuf_slice_mask;
> >  	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> > -		const struct drm_display_mode *adjusted_mode =
> > -			&crtc_state->hw.adjusted_mode;
> > +		const struct drm_display_mode *pipe_mode =
> > +			&crtc_state->hw.pipe_mode;
> >  		enum pipe pipe = crtc->pipe;
> >  		int hdisplay, vdisplay;
> >  		u32 pipe_dbuf_slice_mask;
> > @@ -4205,7 +4205,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> >  		if (dbuf_slice_mask != pipe_dbuf_slice_mask)
> >  			continue;
> >  
> > -		drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
> > +		drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay);
> >  
> >  		total_width_in_range += hdisplay;
> >  
> > @@ -5093,7 +5093,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
> >  	if (drm_WARN_ON(&dev_priv->drm, pixel_rate == 0))
> >  		return u32_to_fixed16(0);
> >  
> > -	crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
> > +	crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal;
> >  	linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
> >  
> >  	return linetime_us;
> > @@ -5282,14 +5282,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> >  	method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
> >  				 wp->cpp, latency, wp->dbuf_block_size);
> >  	method2 = skl_wm_method2(wp->plane_pixel_rate,
> > -				 crtc_state->hw.adjusted_mode.crtc_htotal,
> > +				 crtc_state->hw.pipe_mode.crtc_htotal,
> >  				 latency,
> >  				 wp->plane_blocks_per_line);
> >  
> >  	if (wp->y_tiled) {
> >  		selected_result = max_fixed16(method2, wp->y_tile_minimum);
> >  	} else {
> > -		if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
> > +		if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
> >  		     wp->dbuf_block_size < 1) &&
> >  		     (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
> >  			selected_result = method2;
> > -- 
> > 2.19.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [Intel-gfx] [PATCH v6 3/6] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
  2020-11-05 16:03       ` Navare, Manasi
@ 2020-11-05 16:15         ` Ville Syrjälä
  2020-11-05 18:59           ` Navare, Manasi
  0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2020-11-05 16:15 UTC (permalink / raw)
  To: Navare, Manasi; +Cc: intel-gfx

On Thu, Nov 05, 2020 at 08:03:01AM -0800, Navare, Manasi wrote:
> On Thu, Nov 05, 2020 at 05:13:04PM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 02, 2020 at 03:04:00PM -0800, Manasi Navare wrote:
> > > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > 
> > > With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
> > > because of this, we need a pipe_mode for various calculations, including
> > > for example watermarks, plane clipping, etc.
> > > 
> > > v9:
> > > * pipe_mode in state dump nd state check (Ville)
> > > v8:
> > > * Add pipe_mode in readout in verify_crtc_state (Ville)
> > > v7:
> > > * Remove redundant comment (Ville)
> > > * Just keep mode instead of pipe_mode (Ville)
> > > v6:
> > > * renaming in separate function, only pipe_mode here (Ville)
> > > * Add description (Maarten)
> > > v5:
> > > * Rebase (Manasi)
> > > v4:
> > > * Manual rebase (Manasi)
> > > v3:
> > > * Change state to crtc_state, fix rebase err  (Manasi)
> > > v2:
> > > * Manual Rebase (Manasi)
> > > 
> > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > Reviewed-by: Animesh Manna <animesh.manna@intel.com>
> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c  | 51 ++++++++-----
> > >  .../drm/i915/display/intel_display_types.h    | 11 ++-
> > >  drivers/gpu/drm/i915/intel_pm.c               | 76 +++++++++----------
> > >  3 files changed, 81 insertions(+), 57 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index e9fbcfe1649e..c045ef0ac801 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -6167,18 +6167,16 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> > >  
> > >  static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
> > >  {
> > > -	const struct drm_display_mode *adjusted_mode =
> > > -		&crtc_state->hw.adjusted_mode;
> > > +	const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> > >  	int width, height;
> > >  
> > >  	if (crtc_state->pch_pfit.enabled) {
> > >  		width = drm_rect_width(&crtc_state->pch_pfit.dst);
> > >  		height = drm_rect_height(&crtc_state->pch_pfit.dst);
> > >  	} else {
> > > -		width = adjusted_mode->crtc_hdisplay;
> > > -		height = adjusted_mode->crtc_vdisplay;
> > > +		width = pipe_mode->crtc_hdisplay;
> > > +		height = pipe_mode->crtc_vdisplay;
> > >  	}
> > > -
> > >  	return skl_update_scaler(crtc_state, !crtc_state->hw.active,
> > >  				 SKL_CRTC_INDEX,
> > >  				 &crtc_state->scaler_state.scaler_id,
> > > @@ -8192,7 +8190,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
> > >  
> > >  static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
> > >  {
> > > -	u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
> > > +	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
> > >  	unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
> > >  
> > >  	/*
> > > @@ -8225,7 +8223,11 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
> > >  static void intel_encoder_get_config(struct intel_encoder *encoder,
> > >  				     struct intel_crtc_state *crtc_state)
> > >  {
> > > +	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> > > +
> > >  	encoder->get_config(encoder, crtc_state);
> > > +
> > > +	*pipe_mode = crtc_state->hw.adjusted_mode;
> > >  }
> > >  
> > >  static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> > > @@ -8235,7 +8237,7 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> > >  	if (HAS_GMCH(dev_priv))
> > >  		/* FIXME calculate proper pipe pixel rate for GMCH pfit */
> > >  		crtc_state->pixel_rate =
> > > -			crtc_state->hw.adjusted_mode.crtc_clock;
> > > +			crtc_state->hw.pipe_mode.crtc_clock;
> > >  	else
> > >  		crtc_state->pixel_rate =
> > >  			ilk_pipe_pixel_rate(crtc_state);
> > > @@ -8245,9 +8247,11 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> > >  				     struct intel_crtc_state *pipe_config)
> > >  {
> > >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > -	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> > > +	struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
> > >  	int clock_limit = dev_priv->max_dotclk_freq;
> > >  
> > > +	*pipe_mode = pipe_config->hw.adjusted_mode;
> > 
> > That will now overwrite whatever the encoder computed in
> > .compute_config(). Wasn't that where we wanted to do it for actual
> > bigjoiner, or was that going to be somewhere else?
> 
> We compute the pipe mode for bigjoiner in this function:
> 
> static int intel_crtc_compute_config(struct intel_crtc *crtc,
>                                      struct intel_crtc_state *pipe_config)
> {
>         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>         struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
>         int clock_limit = dev_priv->max_dotclk_freq;
> 
>         *pipe_mode = pipe_config->hw.adjusted_mode;
> 
>         /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
>         if (pipe_config->bigjoiner) {
>                 pipe_mode->crtc_clock /= 2;
>                 pipe_mode->crtc_hdisplay /= 2;
>                 pipe_mode->crtc_hblank_start /= 2;
>                 pipe_mode->crtc_hblank_end /= 2;
>                 pipe_mode->crtc_hsync_start /= 2;
>                 pipe_mode->crtc_hsync_end /= 2;
>                 pipe_mode->crtc_htotal /= 2;
>                 pipe_mode->crtc_hskew /= 2;
>                 pipe_config->pipe_src_w /= 2;
>         }
> 
> So thats why in this patch we just add *pipe_mode = pipe_config->hw.adjusted_mode; the actual big joiner stuff gets added
> in the core big joiner patch : https://patchwork.freedesktop.org/patch/398457/?series=83379&rev=1

OK. In that case this seems fine. Just a bit worried we might need
pipe_mode already before this, in which case doing it earlier would
be required. But we can cross that bridge if/when we come to it.

> 
> 
> > 
> > An alternative would be to do this before .compute_config() +
> > also in intel_fixed_panel_mode() for eDP/etc.
> > 
> > > +
> > >  	if (INTEL_GEN(dev_priv) < 4) {
> > >  		clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
> > >  
> > > @@ -8256,16 +8260,16 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> > >  		 * is > 90% of the (display) core speed.
> > >  		 */
> > >  		if (intel_crtc_supports_double_wide(crtc) &&
> > > -		    adjusted_mode->crtc_clock > clock_limit) {
> > > +		    pipe_mode->crtc_clock > clock_limit) {
> > >  			clock_limit = dev_priv->max_dotclk_freq;
> > >  			pipe_config->double_wide = true;
> > >  		}
> > >  	}
> > >  
> > > -	if (adjusted_mode->crtc_clock > clock_limit) {
> > > +	if (pipe_mode->crtc_clock > clock_limit) {
> > >  		drm_dbg_kms(&dev_priv->drm,
> > >  			    "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
> > > -			    adjusted_mode->crtc_clock, clock_limit,
> > > +			    pipe_mode->crtc_clock, clock_limit,
> > >  			    yesno(pipe_config->double_wide));
> > >  		return -EINVAL;
> > >  	}
> > > @@ -8308,7 +8312,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> > >  	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
> > >  	 */
> > >  	if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
> > > -		adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
> > > +	    pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
> > >  		return -EINVAL;
> > >  
> > >  	intel_crtc_compute_pixel_rate(pipe_config);
> > > @@ -12827,15 +12831,15 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
> > >  
> > >  static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
> > >  {
> > > -	const struct drm_display_mode *adjusted_mode =
> > > -		&crtc_state->hw.adjusted_mode;
> > > +	const struct drm_display_mode *pipe_mode =
> > > +		&crtc_state->hw.pipe_mode;
> > >  	int linetime_wm;
> > >  
> > >  	if (!crtc_state->hw.enable)
> > >  		return 0;
> > >  
> > > -	linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
> > > -					adjusted_mode->crtc_clock);
> > > +	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
> > > +					pipe_mode->crtc_clock);
> > >  
> > >  	return min(linetime_wm, 0x1ff);
> > >  }
> > > @@ -13322,7 +13326,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
> > >  	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> > >  	drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
> > >  	drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
> > > +	drm_dbg_kms(&dev_priv->drm, "pipe mode:\n");
> > > +	drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode);
> > >  	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
> > > +	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
> > >  	drm_dbg_kms(&dev_priv->drm,
> > >  		    "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
> > >  		    pipe_config->port_clock,
> > > @@ -13465,8 +13472,9 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
> > >  	crtc_state->hw.enable = crtc_state->uapi.enable;
> > >  	crtc_state->hw.active = crtc_state->uapi.active;
> > >  	crtc_state->hw.mode = crtc_state->uapi.mode;
> > > -	crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
> > > +	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
> > >  	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
> > > +
> > >  	intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
> > >  }
> > >  
> > > @@ -13663,6 +13671,9 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> > >  		    "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
> > >  		    base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
> > >  
> > > +	/* without bigjoiner, pipe_mode == adjusted_mode */
> > > +	pipe_config->hw.pipe_mode = pipe_config->hw.adjusted_mode;
> > > +
> > >  	return 0;
> > >  }
> > >  
> > > @@ -14071,6 +14082,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > >  
> > >  	PIPE_CONF_CHECK_X(output_types);
> > >  
> > > +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > > +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > > +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > > +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > >  	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> > >  	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> > >  	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> > > @@ -18920,6 +18935,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> > >  			 */
> > >  			crtc_state->inherited = true;
> > >  
> > > +			crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode;
> > > +
> > 
> > Isn't this redundant now?
> 
> Why is this redundant? I think we need this because then intel_crtc_compute_pixel_rate() call actually uses pipe_mode
> for getting pixel rate.

intel_encoder_get_config() already did the copy no?

Hmm. But there is the possibility of BIOS enabling pipes w/o
encoders on older platforms. We may need the extra copy for those.
IIRC we already have some special handling for that in the
.get_pipe_config() implementations, so maybe the pipe_mode copy
should be there as well...

Or, maybe we actually want a intel_crtc_get_pipe_config() wrapper
similar to the intel_encoder_get_config() one you're adding,
which would also do the same copy for us. This might be the
cleanest approach.


> 
> Manasi
> 
> 
> > 
> > >  			intel_crtc_compute_pixel_rate(crtc_state);
> > >  
> > >  			intel_crtc_update_active_timings(crtc_state);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index f6f0626649e0..b526afee595c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -817,15 +817,22 @@ struct intel_crtc_state {
> > >  	 * The following members are used to verify the hardware state:
> > >  	 * - enable
> > >  	 * - active
> > > -	 * - mode / adjusted_mode
> > > +	 * - mode/adjusted_mode
> > >  	 * - color property blobs.
> > >  	 *
> > >  	 * During initial hw readout, they need to be copied to uapi.
> > > +	 *
> > > +	 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
> > > +	 * Use the pipe_mode for calculations like watermarks, pipe
> > > +	 * scaler, and bandwidth.
> > > +	 *
> > > +	 * Use adjusted_mode for things that need to know the full
> > > +	 * mode on the transcoder, which spans all pipes.
> > >  	 */
> > >  	struct {
> > >  		bool active, enable;
> > >  		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
> > > -		struct drm_display_mode mode, adjusted_mode;
> > > +		struct drm_display_mode mode, pipe_mode, adjusted_mode;
> > >  		enum drm_scaling_filter scaling_filter;
> > >  	} hw;
> > >  
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index f54375b11964..9898c257d3e0 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -899,12 +899,12 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc)
> > >  
> > >  	crtc = single_enabled_crtc(dev_priv);
> > >  	if (crtc) {
> > > -		const struct drm_display_mode *adjusted_mode =
> > > -			&crtc->config->hw.adjusted_mode;
> > > +		const struct drm_display_mode *pipe_mode =
> > > +			&crtc->config->hw.pipe_mode;
> > >  		const struct drm_framebuffer *fb =
> > >  			crtc->base.primary->state->fb;
> > >  		int cpp = fb->format->cpp[0];
> > > -		int clock = adjusted_mode->crtc_clock;
> > > +		int clock = pipe_mode->crtc_clock;
> > >  
> > >  		/* Display SR */
> > >  		wm = intel_calculate_wm(clock, &pnv_display_wm,
> > > @@ -1135,8 +1135,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> > >  {
> > >  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > -	const struct drm_display_mode *adjusted_mode =
> > > -		&crtc_state->hw.adjusted_mode;
> > > +	const struct drm_display_mode *pipe_mode =
> > > +		&crtc_state->hw.pipe_mode;
> > >  	unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
> > >  	unsigned int clock, htotal, cpp, width, wm;
> > >  
> > > @@ -1163,8 +1163,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> > >  	    level != G4X_WM_LEVEL_NORMAL)
> > >  		cpp = max(cpp, 4u);
> > >  
> > > -	clock = adjusted_mode->crtc_clock;
> > > -	htotal = adjusted_mode->crtc_htotal;
> > > +	clock = pipe_mode->crtc_clock;
> > > +	htotal = pipe_mode->crtc_htotal;
> > >  
> > >  	width = drm_rect_width(&plane_state->uapi.dst);
> > >  
> > > @@ -1660,8 +1660,8 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
> > >  {
> > >  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > -	const struct drm_display_mode *adjusted_mode =
> > > -		&crtc_state->hw.adjusted_mode;
> > > +	const struct drm_display_mode *pipe_mode =
> > > +		&crtc_state->hw.pipe_mode;
> > >  	unsigned int clock, htotal, cpp, width, wm;
> > >  
> > >  	if (dev_priv->wm.pri_latency[level] == 0)
> > > @@ -1671,8 +1671,8 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
> > >  		return 0;
> > >  
> > >  	cpp = plane_state->hw.fb->format->cpp[0];
> > > -	clock = adjusted_mode->crtc_clock;
> > > -	htotal = adjusted_mode->crtc_htotal;
> > > +	clock = pipe_mode->crtc_clock;
> > > +	htotal = pipe_mode->crtc_htotal;
> > >  	width = crtc_state->pipe_src_w;
> > >  
> > >  	if (plane->id == PLANE_CURSOR) {
> > > @@ -2261,12 +2261,12 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
> > >  	if (crtc) {
> > >  		/* self-refresh has much higher latency */
> > >  		static const int sr_latency_ns = 12000;
> > > -		const struct drm_display_mode *adjusted_mode =
> > > -			&crtc->config->hw.adjusted_mode;
> > > +		const struct drm_display_mode *pipe_mode =
> > > +			&crtc->config->hw.pipe_mode;
> > >  		const struct drm_framebuffer *fb =
> > >  			crtc->base.primary->state->fb;
> > > -		int clock = adjusted_mode->crtc_clock;
> > > -		int htotal = adjusted_mode->crtc_htotal;
> > > +		int clock = pipe_mode->crtc_clock;
> > > +		int htotal = pipe_mode->crtc_htotal;
> > >  		int hdisplay = crtc->config->pipe_src_w;
> > >  		int cpp = fb->format->cpp[0];
> > >  		int entries;
> > > @@ -2345,8 +2345,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> > >  	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
> > >  	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
> > >  	if (intel_crtc_active(crtc)) {
> > > -		const struct drm_display_mode *adjusted_mode =
> > > -			&crtc->config->hw.adjusted_mode;
> > > +		const struct drm_display_mode *pipe_mode =
> > > +			&crtc->config->hw.pipe_mode;
> > >  		const struct drm_framebuffer *fb =
> > >  			crtc->base.primary->state->fb;
> > >  		int cpp;
> > > @@ -2356,7 +2356,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> > >  		else
> > >  			cpp = fb->format->cpp[0];
> > >  
> > > -		planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> > > +		planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
> > >  					       wm_info, fifo_size, cpp,
> > >  					       pessimal_latency_ns);
> > >  		enabled = crtc;
> > > @@ -2372,8 +2372,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> > >  	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
> > >  	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
> > >  	if (intel_crtc_active(crtc)) {
> > > -		const struct drm_display_mode *adjusted_mode =
> > > -			&crtc->config->hw.adjusted_mode;
> > > +		const struct drm_display_mode *pipe_mode =
> > > +			&crtc->config->hw.pipe_mode;
> > >  		const struct drm_framebuffer *fb =
> > >  			crtc->base.primary->state->fb;
> > >  		int cpp;
> > > @@ -2383,7 +2383,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> > >  		else
> > >  			cpp = fb->format->cpp[0];
> > >  
> > > -		planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> > > +		planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
> > >  					       wm_info, fifo_size, cpp,
> > >  					       pessimal_latency_ns);
> > >  		if (enabled == NULL)
> > > @@ -2421,12 +2421,12 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> > >  	if (HAS_FW_BLC(dev_priv) && enabled) {
> > >  		/* self-refresh has much higher latency */
> > >  		static const int sr_latency_ns = 6000;
> > > -		const struct drm_display_mode *adjusted_mode =
> > > -			&enabled->config->hw.adjusted_mode;
> > > +		const struct drm_display_mode *pipe_mode =
> > > +			&enabled->config->hw.pipe_mode;
> > >  		const struct drm_framebuffer *fb =
> > >  			enabled->base.primary->state->fb;
> > > -		int clock = adjusted_mode->crtc_clock;
> > > -		int htotal = adjusted_mode->crtc_htotal;
> > > +		int clock = pipe_mode->crtc_clock;
> > > +		int htotal = pipe_mode->crtc_htotal;
> > >  		int hdisplay = enabled->config->pipe_src_w;
> > >  		int cpp;
> > >  		int entries;
> > > @@ -2474,7 +2474,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
> > >  {
> > >  	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
> > >  	struct intel_crtc *crtc;
> > > -	const struct drm_display_mode *adjusted_mode;
> > > +	const struct drm_display_mode *pipe_mode;
> > >  	u32 fwater_lo;
> > >  	int planea_wm;
> > >  
> > > @@ -2482,8 +2482,8 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
> > >  	if (crtc == NULL)
> > >  		return;
> > >  
> > > -	adjusted_mode = &crtc->config->hw.adjusted_mode;
> > > -	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> > > +	pipe_mode = &crtc->config->hw.pipe_mode;
> > > +	planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
> > >  				       &i845_wm_info,
> > >  				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
> > >  				       4, pessimal_latency_ns);
> > > @@ -2573,7 +2573,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
> > >  		return method1;
> > >  
> > >  	method2 = ilk_wm_method2(crtc_state->pixel_rate,
> > > -				 crtc_state->hw.adjusted_mode.crtc_htotal,
> > > +				 crtc_state->hw.pipe_mode.crtc_htotal,
> > >  				 drm_rect_width(&plane_state->uapi.dst),
> > >  				 cpp, mem_value);
> > >  
> > > @@ -2601,7 +2601,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
> > >  
> > >  	method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
> > >  	method2 = ilk_wm_method2(crtc_state->pixel_rate,
> > > -				 crtc_state->hw.adjusted_mode.crtc_htotal,
> > > +				 crtc_state->hw.pipe_mode.crtc_htotal,
> > >  				 drm_rect_width(&plane_state->uapi.dst),
> > >  				 cpp, mem_value);
> > >  	return min(method1, method2);
> > > @@ -2626,7 +2626,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
> > >  	cpp = plane_state->hw.fb->format->cpp[0];
> > >  
> > >  	return ilk_wm_method2(crtc_state->pixel_rate,
> > > -			      crtc_state->hw.adjusted_mode.crtc_htotal,
> > > +			      crtc_state->hw.pipe_mode.crtc_htotal,
> > >  			      drm_rect_width(&plane_state->uapi.dst),
> > >  			      cpp, mem_value);
> > >  }
> > > @@ -3883,7 +3883,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > >  	if (!crtc_state->hw.active)
> > >  		return true;
> > >  
> > > -	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > > +	if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > >  		return false;
> > >  
> > >  	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> > > @@ -4174,8 +4174,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> > >  	 */
> > >  	total_slice_mask = dbuf_slice_mask;
> > >  	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> > > -		const struct drm_display_mode *adjusted_mode =
> > > -			&crtc_state->hw.adjusted_mode;
> > > +		const struct drm_display_mode *pipe_mode =
> > > +			&crtc_state->hw.pipe_mode;
> > >  		enum pipe pipe = crtc->pipe;
> > >  		int hdisplay, vdisplay;
> > >  		u32 pipe_dbuf_slice_mask;
> > > @@ -4205,7 +4205,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> > >  		if (dbuf_slice_mask != pipe_dbuf_slice_mask)
> > >  			continue;
> > >  
> > > -		drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
> > > +		drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay);
> > >  
> > >  		total_width_in_range += hdisplay;
> > >  
> > > @@ -5093,7 +5093,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
> > >  	if (drm_WARN_ON(&dev_priv->drm, pixel_rate == 0))
> > >  		return u32_to_fixed16(0);
> > >  
> > > -	crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
> > > +	crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal;
> > >  	linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
> > >  
> > >  	return linetime_us;
> > > @@ -5282,14 +5282,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> > >  	method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
> > >  				 wp->cpp, latency, wp->dbuf_block_size);
> > >  	method2 = skl_wm_method2(wp->plane_pixel_rate,
> > > -				 crtc_state->hw.adjusted_mode.crtc_htotal,
> > > +				 crtc_state->hw.pipe_mode.crtc_htotal,
> > >  				 latency,
> > >  				 wp->plane_blocks_per_line);
> > >  
> > >  	if (wp->y_tiled) {
> > >  		selected_result = max_fixed16(method2, wp->y_tile_minimum);
> > >  	} else {
> > > -		if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
> > > +		if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
> > >  		     wp->dbuf_block_size < 1) &&
> > >  		     (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
> > >  			selected_result = method2;
> > > -- 
> > > 2.19.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Ville Syrjälä
> > Intel

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [Intel-gfx] [PATCH v6 3/6] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
  2020-11-05 16:15         ` Ville Syrjälä
@ 2020-11-05 18:59           ` Navare, Manasi
  0 siblings, 0 replies; 32+ messages in thread
From: Navare, Manasi @ 2020-11-05 18:59 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Thu, Nov 05, 2020 at 06:15:11PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 05, 2020 at 08:03:01AM -0800, Navare, Manasi wrote:
> > On Thu, Nov 05, 2020 at 05:13:04PM +0200, Ville Syrjälä wrote:
> > > On Mon, Nov 02, 2020 at 03:04:00PM -0800, Manasi Navare wrote:
> > > > From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > 
> > > > With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
> > > > because of this, we need a pipe_mode for various calculations, including
> > > > for example watermarks, plane clipping, etc.
> > > > 
> > > > v9:
> > > > * pipe_mode in state dump nd state check (Ville)
> > > > v8:
> > > > * Add pipe_mode in readout in verify_crtc_state (Ville)
> > > > v7:
> > > > * Remove redundant comment (Ville)
> > > > * Just keep mode instead of pipe_mode (Ville)
> > > > v6:
> > > > * renaming in separate function, only pipe_mode here (Ville)
> > > > * Add description (Maarten)
> > > > v5:
> > > > * Rebase (Manasi)
> > > > v4:
> > > > * Manual rebase (Manasi)
> > > > v3:
> > > > * Change state to crtc_state, fix rebase err  (Manasi)
> > > > v2:
> > > > * Manual Rebase (Manasi)
> > > > 
> > > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > > Reviewed-by: Animesh Manna <animesh.manna@intel.com>
> > > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_display.c  | 51 ++++++++-----
> > > >  .../drm/i915/display/intel_display_types.h    | 11 ++-
> > > >  drivers/gpu/drm/i915/intel_pm.c               | 76 +++++++++----------
> > > >  3 files changed, 81 insertions(+), 57 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index e9fbcfe1649e..c045ef0ac801 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -6167,18 +6167,16 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> > > >  
> > > >  static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
> > > >  {
> > > > -	const struct drm_display_mode *adjusted_mode =
> > > > -		&crtc_state->hw.adjusted_mode;
> > > > +	const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> > > >  	int width, height;
> > > >  
> > > >  	if (crtc_state->pch_pfit.enabled) {
> > > >  		width = drm_rect_width(&crtc_state->pch_pfit.dst);
> > > >  		height = drm_rect_height(&crtc_state->pch_pfit.dst);
> > > >  	} else {
> > > > -		width = adjusted_mode->crtc_hdisplay;
> > > > -		height = adjusted_mode->crtc_vdisplay;
> > > > +		width = pipe_mode->crtc_hdisplay;
> > > > +		height = pipe_mode->crtc_vdisplay;
> > > >  	}
> > > > -
> > > >  	return skl_update_scaler(crtc_state, !crtc_state->hw.active,
> > > >  				 SKL_CRTC_INDEX,
> > > >  				 &crtc_state->scaler_state.scaler_id,
> > > > @@ -8192,7 +8190,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
> > > >  
> > > >  static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
> > > >  {
> > > > -	u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
> > > > +	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
> > > >  	unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
> > > >  
> > > >  	/*
> > > > @@ -8225,7 +8223,11 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
> > > >  static void intel_encoder_get_config(struct intel_encoder *encoder,
> > > >  				     struct intel_crtc_state *crtc_state)
> > > >  {
> > > > +	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
> > > > +
> > > >  	encoder->get_config(encoder, crtc_state);
> > > > +
> > > > +	*pipe_mode = crtc_state->hw.adjusted_mode;
> > > >  }
> > > >  
> > > >  static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> > > > @@ -8235,7 +8237,7 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> > > >  	if (HAS_GMCH(dev_priv))
> > > >  		/* FIXME calculate proper pipe pixel rate for GMCH pfit */
> > > >  		crtc_state->pixel_rate =
> > > > -			crtc_state->hw.adjusted_mode.crtc_clock;
> > > > +			crtc_state->hw.pipe_mode.crtc_clock;
> > > >  	else
> > > >  		crtc_state->pixel_rate =
> > > >  			ilk_pipe_pixel_rate(crtc_state);
> > > > @@ -8245,9 +8247,11 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> > > >  				     struct intel_crtc_state *pipe_config)
> > > >  {
> > > >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > > -	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> > > > +	struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
> > > >  	int clock_limit = dev_priv->max_dotclk_freq;
> > > >  
> > > > +	*pipe_mode = pipe_config->hw.adjusted_mode;
> > > 
> > > That will now overwrite whatever the encoder computed in
> > > .compute_config(). Wasn't that where we wanted to do it for actual
> > > bigjoiner, or was that going to be somewhere else?
> > 
> > We compute the pipe mode for bigjoiner in this function:
> > 
> > static int intel_crtc_compute_config(struct intel_crtc *crtc,
> >                                      struct intel_crtc_state *pipe_config)
> > {
> >         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >         struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
> >         int clock_limit = dev_priv->max_dotclk_freq;
> > 
> >         *pipe_mode = pipe_config->hw.adjusted_mode;
> > 
> >         /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
> >         if (pipe_config->bigjoiner) {
> >                 pipe_mode->crtc_clock /= 2;
> >                 pipe_mode->crtc_hdisplay /= 2;
> >                 pipe_mode->crtc_hblank_start /= 2;
> >                 pipe_mode->crtc_hblank_end /= 2;
> >                 pipe_mode->crtc_hsync_start /= 2;
> >                 pipe_mode->crtc_hsync_end /= 2;
> >                 pipe_mode->crtc_htotal /= 2;
> >                 pipe_mode->crtc_hskew /= 2;
> >                 pipe_config->pipe_src_w /= 2;
> >         }
> > 
> > So thats why in this patch we just add *pipe_mode = pipe_config->hw.adjusted_mode; the actual big joiner stuff gets added
> > in the core big joiner patch : https://patchwork.freedesktop.org/patch/398457/?series=83379&rev=1
> 
> OK. In that case this seems fine. Just a bit worried we might need
> pipe_mode already before this, in which case doing it earlier would
> be required. But we can cross that bridge if/when we come to it.
> 
> > 
> > 
> > > 
> > > An alternative would be to do this before .compute_config() +
> > > also in intel_fixed_panel_mode() for eDP/etc.
> > > 
> > > > +
> > > >  	if (INTEL_GEN(dev_priv) < 4) {
> > > >  		clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
> > > >  
> > > > @@ -8256,16 +8260,16 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> > > >  		 * is > 90% of the (display) core speed.
> > > >  		 */
> > > >  		if (intel_crtc_supports_double_wide(crtc) &&
> > > > -		    adjusted_mode->crtc_clock > clock_limit) {
> > > > +		    pipe_mode->crtc_clock > clock_limit) {
> > > >  			clock_limit = dev_priv->max_dotclk_freq;
> > > >  			pipe_config->double_wide = true;
> > > >  		}
> > > >  	}
> > > >  
> > > > -	if (adjusted_mode->crtc_clock > clock_limit) {
> > > > +	if (pipe_mode->crtc_clock > clock_limit) {
> > > >  		drm_dbg_kms(&dev_priv->drm,
> > > >  			    "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
> > > > -			    adjusted_mode->crtc_clock, clock_limit,
> > > > +			    pipe_mode->crtc_clock, clock_limit,
> > > >  			    yesno(pipe_config->double_wide));
> > > >  		return -EINVAL;
> > > >  	}
> > > > @@ -8308,7 +8312,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> > > >  	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
> > > >  	 */
> > > >  	if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
> > > > -		adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
> > > > +	    pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
> > > >  		return -EINVAL;
> > > >  
> > > >  	intel_crtc_compute_pixel_rate(pipe_config);
> > > > @@ -12827,15 +12831,15 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
> > > >  
> > > >  static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
> > > >  {
> > > > -	const struct drm_display_mode *adjusted_mode =
> > > > -		&crtc_state->hw.adjusted_mode;
> > > > +	const struct drm_display_mode *pipe_mode =
> > > > +		&crtc_state->hw.pipe_mode;
> > > >  	int linetime_wm;
> > > >  
> > > >  	if (!crtc_state->hw.enable)
> > > >  		return 0;
> > > >  
> > > > -	linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
> > > > -					adjusted_mode->crtc_clock);
> > > > +	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
> > > > +					pipe_mode->crtc_clock);
> > > >  
> > > >  	return min(linetime_wm, 0x1ff);
> > > >  }
> > > > @@ -13322,7 +13326,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
> > > >  	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> > > >  	drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
> > > >  	drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
> > > > +	drm_dbg_kms(&dev_priv->drm, "pipe mode:\n");
> > > > +	drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode);
> > > >  	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
> > > > +	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
> > > >  	drm_dbg_kms(&dev_priv->drm,
> > > >  		    "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
> > > >  		    pipe_config->port_clock,
> > > > @@ -13465,8 +13472,9 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
> > > >  	crtc_state->hw.enable = crtc_state->uapi.enable;
> > > >  	crtc_state->hw.active = crtc_state->uapi.active;
> > > >  	crtc_state->hw.mode = crtc_state->uapi.mode;
> > > > -	crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
> > > > +	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
> > > >  	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
> > > > +
> > > >  	intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
> > > >  }
> > > >  
> > > > @@ -13663,6 +13671,9 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> > > >  		    "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
> > > >  		    base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
> > > >  
> > > > +	/* without bigjoiner, pipe_mode == adjusted_mode */
> > > > +	pipe_config->hw.pipe_mode = pipe_config->hw.adjusted_mode;
> > > > +
> > > >  	return 0;
> > > >  }
> > > >  
> > > > @@ -14071,6 +14082,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> > > >  
> > > >  	PIPE_CONF_CHECK_X(output_types);
> > > >  
> > > > +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > > > +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > > > +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > > > +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> > > >  	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> > > >  	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> > > >  	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> > > > @@ -18920,6 +18935,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> > > >  			 */
> > > >  			crtc_state->inherited = true;
> > > >  
> > > > +			crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode;
> > > > +
> > > 
> > > Isn't this redundant now?
> > 
> > Why is this redundant? I think we need this because then intel_crtc_compute_pixel_rate() call actually uses pipe_mode
> > for getting pixel rate.
> 
> intel_encoder_get_config() already did the copy no?
> 
> Hmm. But there is the possibility of BIOS enabling pipes w/o
> encoders on older platforms. We may need the extra copy for those.
> IIRC we already have some special handling for that in the
> .get_pipe_config() implementations, so maybe the pipe_mode copy
> should be there as well...
> 
> Or, maybe we actually want a intel_crtc_get_pipe_config() wrapper
> similar to the intel_encoder_get_config() one you're adding,
> which would also do the same copy for us. This might be the
> cleanest approach.
>

Okay yes I can create a new intel_crtc_get_config() something like below:

static bool intel_crtc_get_pipe_config()
{
	dev_priv->display.get_pipe_config(crtc, pipe_config);
	pipe_config->hw.pipe_mode = crtc_state->hw.adjusted_mode;
}

Looks fine right?

Manasi

} 
> 
> > 
> > Manasi
> > 
> > 
> > > 
> > > >  			intel_crtc_compute_pixel_rate(crtc_state);
> > > >  
> > > >  			intel_crtc_update_active_timings(crtc_state);
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index f6f0626649e0..b526afee595c 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -817,15 +817,22 @@ struct intel_crtc_state {
> > > >  	 * The following members are used to verify the hardware state:
> > > >  	 * - enable
> > > >  	 * - active
> > > > -	 * - mode / adjusted_mode
> > > > +	 * - mode/adjusted_mode
> > > >  	 * - color property blobs.
> > > >  	 *
> > > >  	 * During initial hw readout, they need to be copied to uapi.
> > > > +	 *
> > > > +	 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
> > > > +	 * Use the pipe_mode for calculations like watermarks, pipe
> > > > +	 * scaler, and bandwidth.
> > > > +	 *
> > > > +	 * Use adjusted_mode for things that need to know the full
> > > > +	 * mode on the transcoder, which spans all pipes.
> > > >  	 */
> > > >  	struct {
> > > >  		bool active, enable;
> > > >  		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
> > > > -		struct drm_display_mode mode, adjusted_mode;
> > > > +		struct drm_display_mode mode, pipe_mode, adjusted_mode;
> > > >  		enum drm_scaling_filter scaling_filter;
> > > >  	} hw;
> > > >  
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index f54375b11964..9898c257d3e0 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -899,12 +899,12 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc)
> > > >  
> > > >  	crtc = single_enabled_crtc(dev_priv);
> > > >  	if (crtc) {
> > > > -		const struct drm_display_mode *adjusted_mode =
> > > > -			&crtc->config->hw.adjusted_mode;
> > > > +		const struct drm_display_mode *pipe_mode =
> > > > +			&crtc->config->hw.pipe_mode;
> > > >  		const struct drm_framebuffer *fb =
> > > >  			crtc->base.primary->state->fb;
> > > >  		int cpp = fb->format->cpp[0];
> > > > -		int clock = adjusted_mode->crtc_clock;
> > > > +		int clock = pipe_mode->crtc_clock;
> > > >  
> > > >  		/* Display SR */
> > > >  		wm = intel_calculate_wm(clock, &pnv_display_wm,
> > > > @@ -1135,8 +1135,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> > > >  {
> > > >  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> > > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > > -	const struct drm_display_mode *adjusted_mode =
> > > > -		&crtc_state->hw.adjusted_mode;
> > > > +	const struct drm_display_mode *pipe_mode =
> > > > +		&crtc_state->hw.pipe_mode;
> > > >  	unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
> > > >  	unsigned int clock, htotal, cpp, width, wm;
> > > >  
> > > > @@ -1163,8 +1163,8 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> > > >  	    level != G4X_WM_LEVEL_NORMAL)
> > > >  		cpp = max(cpp, 4u);
> > > >  
> > > > -	clock = adjusted_mode->crtc_clock;
> > > > -	htotal = adjusted_mode->crtc_htotal;
> > > > +	clock = pipe_mode->crtc_clock;
> > > > +	htotal = pipe_mode->crtc_htotal;
> > > >  
> > > >  	width = drm_rect_width(&plane_state->uapi.dst);
> > > >  
> > > > @@ -1660,8 +1660,8 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
> > > >  {
> > > >  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> > > >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > > -	const struct drm_display_mode *adjusted_mode =
> > > > -		&crtc_state->hw.adjusted_mode;
> > > > +	const struct drm_display_mode *pipe_mode =
> > > > +		&crtc_state->hw.pipe_mode;
> > > >  	unsigned int clock, htotal, cpp, width, wm;
> > > >  
> > > >  	if (dev_priv->wm.pri_latency[level] == 0)
> > > > @@ -1671,8 +1671,8 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
> > > >  		return 0;
> > > >  
> > > >  	cpp = plane_state->hw.fb->format->cpp[0];
> > > > -	clock = adjusted_mode->crtc_clock;
> > > > -	htotal = adjusted_mode->crtc_htotal;
> > > > +	clock = pipe_mode->crtc_clock;
> > > > +	htotal = pipe_mode->crtc_htotal;
> > > >  	width = crtc_state->pipe_src_w;
> > > >  
> > > >  	if (plane->id == PLANE_CURSOR) {
> > > > @@ -2261,12 +2261,12 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
> > > >  	if (crtc) {
> > > >  		/* self-refresh has much higher latency */
> > > >  		static const int sr_latency_ns = 12000;
> > > > -		const struct drm_display_mode *adjusted_mode =
> > > > -			&crtc->config->hw.adjusted_mode;
> > > > +		const struct drm_display_mode *pipe_mode =
> > > > +			&crtc->config->hw.pipe_mode;
> > > >  		const struct drm_framebuffer *fb =
> > > >  			crtc->base.primary->state->fb;
> > > > -		int clock = adjusted_mode->crtc_clock;
> > > > -		int htotal = adjusted_mode->crtc_htotal;
> > > > +		int clock = pipe_mode->crtc_clock;
> > > > +		int htotal = pipe_mode->crtc_htotal;
> > > >  		int hdisplay = crtc->config->pipe_src_w;
> > > >  		int cpp = fb->format->cpp[0];
> > > >  		int entries;
> > > > @@ -2345,8 +2345,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> > > >  	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
> > > >  	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
> > > >  	if (intel_crtc_active(crtc)) {
> > > > -		const struct drm_display_mode *adjusted_mode =
> > > > -			&crtc->config->hw.adjusted_mode;
> > > > +		const struct drm_display_mode *pipe_mode =
> > > > +			&crtc->config->hw.pipe_mode;
> > > >  		const struct drm_framebuffer *fb =
> > > >  			crtc->base.primary->state->fb;
> > > >  		int cpp;
> > > > @@ -2356,7 +2356,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> > > >  		else
> > > >  			cpp = fb->format->cpp[0];
> > > >  
> > > > -		planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> > > > +		planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
> > > >  					       wm_info, fifo_size, cpp,
> > > >  					       pessimal_latency_ns);
> > > >  		enabled = crtc;
> > > > @@ -2372,8 +2372,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> > > >  	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
> > > >  	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
> > > >  	if (intel_crtc_active(crtc)) {
> > > > -		const struct drm_display_mode *adjusted_mode =
> > > > -			&crtc->config->hw.adjusted_mode;
> > > > +		const struct drm_display_mode *pipe_mode =
> > > > +			&crtc->config->hw.pipe_mode;
> > > >  		const struct drm_framebuffer *fb =
> > > >  			crtc->base.primary->state->fb;
> > > >  		int cpp;
> > > > @@ -2383,7 +2383,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> > > >  		else
> > > >  			cpp = fb->format->cpp[0];
> > > >  
> > > > -		planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> > > > +		planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
> > > >  					       wm_info, fifo_size, cpp,
> > > >  					       pessimal_latency_ns);
> > > >  		if (enabled == NULL)
> > > > @@ -2421,12 +2421,12 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> > > >  	if (HAS_FW_BLC(dev_priv) && enabled) {
> > > >  		/* self-refresh has much higher latency */
> > > >  		static const int sr_latency_ns = 6000;
> > > > -		const struct drm_display_mode *adjusted_mode =
> > > > -			&enabled->config->hw.adjusted_mode;
> > > > +		const struct drm_display_mode *pipe_mode =
> > > > +			&enabled->config->hw.pipe_mode;
> > > >  		const struct drm_framebuffer *fb =
> > > >  			enabled->base.primary->state->fb;
> > > > -		int clock = adjusted_mode->crtc_clock;
> > > > -		int htotal = adjusted_mode->crtc_htotal;
> > > > +		int clock = pipe_mode->crtc_clock;
> > > > +		int htotal = pipe_mode->crtc_htotal;
> > > >  		int hdisplay = enabled->config->pipe_src_w;
> > > >  		int cpp;
> > > >  		int entries;
> > > > @@ -2474,7 +2474,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
> > > >  {
> > > >  	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
> > > >  	struct intel_crtc *crtc;
> > > > -	const struct drm_display_mode *adjusted_mode;
> > > > +	const struct drm_display_mode *pipe_mode;
> > > >  	u32 fwater_lo;
> > > >  	int planea_wm;
> > > >  
> > > > @@ -2482,8 +2482,8 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
> > > >  	if (crtc == NULL)
> > > >  		return;
> > > >  
> > > > -	adjusted_mode = &crtc->config->hw.adjusted_mode;
> > > > -	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> > > > +	pipe_mode = &crtc->config->hw.pipe_mode;
> > > > +	planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
> > > >  				       &i845_wm_info,
> > > >  				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
> > > >  				       4, pessimal_latency_ns);
> > > > @@ -2573,7 +2573,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
> > > >  		return method1;
> > > >  
> > > >  	method2 = ilk_wm_method2(crtc_state->pixel_rate,
> > > > -				 crtc_state->hw.adjusted_mode.crtc_htotal,
> > > > +				 crtc_state->hw.pipe_mode.crtc_htotal,
> > > >  				 drm_rect_width(&plane_state->uapi.dst),
> > > >  				 cpp, mem_value);
> > > >  
> > > > @@ -2601,7 +2601,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
> > > >  
> > > >  	method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
> > > >  	method2 = ilk_wm_method2(crtc_state->pixel_rate,
> > > > -				 crtc_state->hw.adjusted_mode.crtc_htotal,
> > > > +				 crtc_state->hw.pipe_mode.crtc_htotal,
> > > >  				 drm_rect_width(&plane_state->uapi.dst),
> > > >  				 cpp, mem_value);
> > > >  	return min(method1, method2);
> > > > @@ -2626,7 +2626,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
> > > >  	cpp = plane_state->hw.fb->format->cpp[0];
> > > >  
> > > >  	return ilk_wm_method2(crtc_state->pixel_rate,
> > > > -			      crtc_state->hw.adjusted_mode.crtc_htotal,
> > > > +			      crtc_state->hw.pipe_mode.crtc_htotal,
> > > >  			      drm_rect_width(&plane_state->uapi.dst),
> > > >  			      cpp, mem_value);
> > > >  }
> > > > @@ -3883,7 +3883,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > >  	if (!crtc_state->hw.active)
> > > >  		return true;
> > > >  
> > > > -	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > > > +	if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > > >  		return false;
> > > >  
> > > >  	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> > > > @@ -4174,8 +4174,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> > > >  	 */
> > > >  	total_slice_mask = dbuf_slice_mask;
> > > >  	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> > > > -		const struct drm_display_mode *adjusted_mode =
> > > > -			&crtc_state->hw.adjusted_mode;
> > > > +		const struct drm_display_mode *pipe_mode =
> > > > +			&crtc_state->hw.pipe_mode;
> > > >  		enum pipe pipe = crtc->pipe;
> > > >  		int hdisplay, vdisplay;
> > > >  		u32 pipe_dbuf_slice_mask;
> > > > @@ -4205,7 +4205,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> > > >  		if (dbuf_slice_mask != pipe_dbuf_slice_mask)
> > > >  			continue;
> > > >  
> > > > -		drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
> > > > +		drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay);
> > > >  
> > > >  		total_width_in_range += hdisplay;
> > > >  
> > > > @@ -5093,7 +5093,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
> > > >  	if (drm_WARN_ON(&dev_priv->drm, pixel_rate == 0))
> > > >  		return u32_to_fixed16(0);
> > > >  
> > > > -	crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
> > > > +	crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal;
> > > >  	linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
> > > >  
> > > >  	return linetime_us;
> > > > @@ -5282,14 +5282,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> > > >  	method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
> > > >  				 wp->cpp, latency, wp->dbuf_block_size);
> > > >  	method2 = skl_wm_method2(wp->plane_pixel_rate,
> > > > -				 crtc_state->hw.adjusted_mode.crtc_htotal,
> > > > +				 crtc_state->hw.pipe_mode.crtc_htotal,
> > > >  				 latency,
> > > >  				 wp->plane_blocks_per_line);
> > > >  
> > > >  	if (wp->y_tiled) {
> > > >  		selected_result = max_fixed16(method2, wp->y_tile_minimum);
> > > >  	} else {
> > > > -		if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
> > > > +		if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
> > > >  		     wp->dbuf_block_size < 1) &&
> > > >  		     (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
> > > >  			selected_result = method2;
> > > > -- 
> > > > 2.19.1
> > > > 
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > 
> > > -- 
> > > Ville Syrjälä
> > > Intel
> 
> -- 
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] [PATCH v5 4/6] drm/i915: Pass intel_atomic_state instead of drm_atomic_state
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 2/6] drm/i915: Move encoder->get_config to a new function Manasi Navare
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 3/6] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split Manasi Navare
@ 2020-11-02 21:19 ` Manasi Navare
  2020-11-05 15:14   ` Ville Syrjälä
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 5/6] drm/i915/dp: Prep for bigjoiner atomic check Manasi Navare
                   ` (12 subsequent siblings)
  15 siblings, 1 reply; 32+ messages in thread
From: Manasi Navare @ 2020-11-02 21:19 UTC (permalink / raw)
  To: intel-gfx

No functional changes, to align with previous cleanups pass
intel_atomic_state instead of drm_atomic_state.
Also pass this intel_atomic_state with crtc_state to
some of the atomic_check functions.

Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e8cdfab69c91..0bea90cdf242 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12671,7 +12671,7 @@ static bool encoders_cloneable(const struct intel_encoder *a,
 			  b->cloneable & (1 << a->type));
 }
 
-static bool check_single_encoder_cloning(struct drm_atomic_state *state,
+static bool check_single_encoder_cloning(struct intel_atomic_state *state,
 					 struct intel_crtc *crtc,
 					 struct intel_encoder *encoder)
 {
@@ -12680,7 +12680,7 @@ static bool check_single_encoder_cloning(struct drm_atomic_state *state,
 	struct drm_connector_state *connector_state;
 	int i;
 
-	for_each_new_connector_in_state(state, connector, connector_state, i) {
+	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
 		if (connector_state->crtc != &crtc->base)
 			continue;
 
@@ -13534,10 +13534,10 @@ intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
 }
 
 static int
-intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
+intel_modeset_pipe_config(struct intel_atomic_state *state,
+			  struct intel_crtc_state *pipe_config)
 {
 	struct drm_crtc *crtc = pipe_config->uapi.crtc;
-	struct drm_atomic_state *state = pipe_config->uapi.state;
 	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
 	struct drm_connector *connector;
 	struct drm_connector_state *connector_state;
@@ -13579,7 +13579,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
 			       &pipe_config->pipe_src_w,
 			       &pipe_config->pipe_src_h);
 
-	for_each_new_connector_in_state(state, connector, connector_state, i) {
+	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
 		struct intel_encoder *encoder =
 			to_intel_encoder(connector_state->best_encoder);
 
@@ -13617,7 +13617,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
 	 * adjust it according to limitations or connector properties, and also
 	 * a chance to reject the mode entirely.
 	 */
-	for_each_new_connector_in_state(state, connector, connector_state, i) {
+	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
 		struct intel_encoder *encoder =
 			to_intel_encoder(connector_state->best_encoder);
 
@@ -15245,7 +15245,7 @@ static int intel_atomic_check(struct drm_device *dev,
 		if (!new_crtc_state->hw.enable)
 			continue;
 
-		ret = intel_modeset_pipe_config(new_crtc_state);
+		ret = intel_modeset_pipe_config(state, new_crtc_state);
 		if (ret)
 			goto fail;
 	}
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread

* Re: [Intel-gfx] [PATCH v5 4/6] drm/i915: Pass intel_atomic_state instead of drm_atomic_state
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 4/6] drm/i915: Pass intel_atomic_state instead of drm_atomic_state Manasi Navare
@ 2020-11-05 15:14   ` Ville Syrjälä
  0 siblings, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2020-11-05 15:14 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx

On Mon, Nov 02, 2020 at 01:19:04PM -0800, Manasi Navare wrote:
> No functional changes, to align with previous cleanups pass
> intel_atomic_state instead of drm_atomic_state.
> Also pass this intel_atomic_state with crtc_state to
> some of the atomic_check functions.
> 
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e8cdfab69c91..0bea90cdf242 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12671,7 +12671,7 @@ static bool encoders_cloneable(const struct intel_encoder *a,
>  			  b->cloneable & (1 << a->type));
>  }
>  
> -static bool check_single_encoder_cloning(struct drm_atomic_state *state,
> +static bool check_single_encoder_cloning(struct intel_atomic_state *state,
>  					 struct intel_crtc *crtc,
>  					 struct intel_encoder *encoder)
>  {
> @@ -12680,7 +12680,7 @@ static bool check_single_encoder_cloning(struct drm_atomic_state *state,
>  	struct drm_connector_state *connector_state;
>  	int i;
>  
> -	for_each_new_connector_in_state(state, connector, connector_state, i) {
> +	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
>  		if (connector_state->crtc != &crtc->base)
>  			continue;
>  
> @@ -13534,10 +13534,10 @@ intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
>  }
>  
>  static int
> -intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> +intel_modeset_pipe_config(struct intel_atomic_state *state,
> +			  struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_crtc *crtc = pipe_config->uapi.crtc;
> -	struct drm_atomic_state *state = pipe_config->uapi.state;
>  	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
>  	struct drm_connector *connector;
>  	struct drm_connector_state *connector_state;
> @@ -13579,7 +13579,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
>  			       &pipe_config->pipe_src_w,
>  			       &pipe_config->pipe_src_h);
>  
> -	for_each_new_connector_in_state(state, connector, connector_state, i) {
> +	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
>  		struct intel_encoder *encoder =
>  			to_intel_encoder(connector_state->best_encoder);
>  
> @@ -13617,7 +13617,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
>  	 * adjust it according to limitations or connector properties, and also
>  	 * a chance to reject the mode entirely.
>  	 */
> -	for_each_new_connector_in_state(state, connector, connector_state, i) {
> +	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
>  		struct intel_encoder *encoder =
>  			to_intel_encoder(connector_state->best_encoder);
>  
> @@ -15245,7 +15245,7 @@ static int intel_atomic_check(struct drm_device *dev,
>  		if (!new_crtc_state->hw.enable)
>  			continue;
>  
> -		ret = intel_modeset_pipe_config(new_crtc_state);
> +		ret = intel_modeset_pipe_config(state, new_crtc_state);
>  		if (ret)
>  			goto fail;
>  	}
> -- 
> 2.19.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] [PATCH v5 5/6] drm/i915/dp: Prep for bigjoiner atomic check
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
                   ` (2 preceding siblings ...)
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 4/6] drm/i915: Pass intel_atomic_state instead of drm_atomic_state Manasi Navare
@ 2020-11-02 21:19 ` Manasi Navare
  2020-11-05 15:21   ` Ville Syrjälä
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 6/6] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3 Manasi Navare
                   ` (11 subsequent siblings)
  15 siblings, 1 reply; 32+ messages in thread
From: Manasi Navare @ 2020-11-02 21:19 UTC (permalink / raw)
  To: intel-gfx

No functional changes here. Just pass intel_atomic_state
along with crtc_state to certain atomic_check functions.
This will lay the foundation for adding bigjoiner master/slave
states in atomic check.

v2:
* More prep with intel_atomic_state (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic.c  |  9 +++++----
 drivers/gpu/drm/i915/display/intel_atomic.h  |  3 ++-
 drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++--------
 3 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 86be032bcf96..e243ce97b534 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -270,14 +270,15 @@ void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
 	intel_crtc_put_color_blobs(crtc_state);
 }
 
-void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
+				 const struct intel_crtc_state *from_crtc_state)
 {
 	drm_property_replace_blob(&crtc_state->hw.degamma_lut,
-				  crtc_state->uapi.degamma_lut);
+				  from_crtc_state->uapi.degamma_lut);
 	drm_property_replace_blob(&crtc_state->hw.gamma_lut,
-				  crtc_state->uapi.gamma_lut);
+				  from_crtc_state->uapi.gamma_lut);
 	drm_property_replace_blob(&crtc_state->hw.ctm,
-				  crtc_state->uapi.ctm);
+				  from_crtc_state->uapi.ctm);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 285de07011dc..62a3365ed5e6 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -43,7 +43,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
 void intel_crtc_destroy_state(struct drm_crtc *crtc,
 			       struct drm_crtc_state *state);
 void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
-void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
+				 const struct intel_crtc_state *from_crtc_state);
 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
 void intel_atomic_state_free(struct drm_atomic_state *state);
 void intel_atomic_state_clear(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0bea90cdf242..ab10dfe705e4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13459,13 +13459,17 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state)
 }
 
 static void
-intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
+intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
+					   struct intel_crtc_state *crtc_state)
 {
-	intel_crtc_copy_color_blobs(crtc_state);
+	const struct intel_crtc_state *from_crtc_state = crtc_state;
+
+	intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
 }
 
 static void
-intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
+intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
+				 struct intel_crtc_state *crtc_state)
 {
 	crtc_state->hw.enable = crtc_state->uapi.enable;
 	crtc_state->hw.active = crtc_state->uapi.active;
@@ -13473,7 +13477,7 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
 	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
 	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
 
-	intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
+	intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
 }
 
 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
@@ -13496,7 +13500,8 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
 }
 
 static int
-intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
+intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
+				 struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -13528,7 +13533,7 @@ intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
 	memcpy(crtc_state, saved_state, sizeof(*crtc_state));
 	kfree(saved_state);
 
-	intel_crtc_copy_uapi_to_hw_state(crtc_state);
+	intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
 
 	return 0;
 }
@@ -15233,12 +15238,12 @@ static int intel_atomic_check(struct drm_device *dev,
 					    new_crtc_state, i) {
 		if (!needs_modeset(new_crtc_state)) {
 			/* Light copy */
-			intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
+			intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state);
 
 			continue;
 		}
 
-		ret = intel_crtc_prepare_cleared_state(new_crtc_state);
+		ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
 		if (ret)
 			goto fail;
 
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread

* Re: [Intel-gfx] [PATCH v5 5/6] drm/i915/dp: Prep for bigjoiner atomic check
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 5/6] drm/i915/dp: Prep for bigjoiner atomic check Manasi Navare
@ 2020-11-05 15:21   ` Ville Syrjälä
  2020-11-05 15:23     ` Ville Syrjälä
  0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2020-11-05 15:21 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx

On Mon, Nov 02, 2020 at 01:19:05PM -0800, Manasi Navare wrote:
> No functional changes here. Just pass intel_atomic_state
> along with crtc_state to certain atomic_check functions.
> This will lay the foundation for adding bigjoiner master/slave
> states in atomic check.
> 
> v2:
> * More prep with intel_atomic_state (Ville)
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_atomic.c  |  9 +++++----
>  drivers/gpu/drm/i915/display/intel_atomic.h  |  3 ++-
>  drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++--------
>  3 files changed, 20 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 86be032bcf96..e243ce97b534 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -270,14 +270,15 @@ void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
>  	intel_crtc_put_color_blobs(crtc_state);
>  }
>  
> -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> +				 const struct intel_crtc_state *from_crtc_state)
>  {
>  	drm_property_replace_blob(&crtc_state->hw.degamma_lut,
> -				  crtc_state->uapi.degamma_lut);
> +				  from_crtc_state->uapi.degamma_lut);
>  	drm_property_replace_blob(&crtc_state->hw.gamma_lut,
> -				  crtc_state->uapi.gamma_lut);
> +				  from_crtc_state->uapi.gamma_lut);
>  	drm_property_replace_blob(&crtc_state->hw.ctm,
> -				  crtc_state->uapi.ctm);
> +				  from_crtc_state->uapi.ctm);

This patch still seems to do two totally separate things:
1) pass intel_atomic_State all over (for which there was another
   patch in the series as well?)
2) this intel_crtc_copy_color_blobs() change

I would split these up because the commit message doesn't
even mention the second change.

Each part looks fine on its own so with a proper split they are
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 285de07011dc..62a3365ed5e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -43,7 +43,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
>  void intel_crtc_destroy_state(struct drm_crtc *crtc,
>  			       struct drm_crtc_state *state);
>  void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
> -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> +				 const struct intel_crtc_state *from_crtc_state);
>  struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
>  void intel_atomic_state_free(struct drm_atomic_state *state);
>  void intel_atomic_state_clear(struct drm_atomic_state *state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0bea90cdf242..ab10dfe705e4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13459,13 +13459,17 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state)
>  }
>  
>  static void
> -intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
> +intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
> +					   struct intel_crtc_state *crtc_state)
>  {
> -	intel_crtc_copy_color_blobs(crtc_state);
> +	const struct intel_crtc_state *from_crtc_state = crtc_state;
> +
> +	intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
>  }
>  
>  static void
> -intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
> +intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
> +				 struct intel_crtc_state *crtc_state)
>  {
>  	crtc_state->hw.enable = crtc_state->uapi.enable;
>  	crtc_state->hw.active = crtc_state->uapi.active;
> @@ -13473,7 +13477,7 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
>  	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
>  	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
>  
> -	intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
> +	intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
>  }
>  
>  static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> @@ -13496,7 +13500,8 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
>  }
>  
>  static int
> -intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
> +intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
> +				 struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -13528,7 +13533,7 @@ intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
>  	memcpy(crtc_state, saved_state, sizeof(*crtc_state));
>  	kfree(saved_state);
>  
> -	intel_crtc_copy_uapi_to_hw_state(crtc_state);
> +	intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
>  
>  	return 0;
>  }
> @@ -15233,12 +15238,12 @@ static int intel_atomic_check(struct drm_device *dev,
>  					    new_crtc_state, i) {
>  		if (!needs_modeset(new_crtc_state)) {
>  			/* Light copy */
> -			intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
> +			intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state);
>  
>  			continue;
>  		}
>  
> -		ret = intel_crtc_prepare_cleared_state(new_crtc_state);
> +		ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
>  		if (ret)
>  			goto fail;
>  
> -- 
> 2.19.1

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [Intel-gfx] [PATCH v5 5/6] drm/i915/dp: Prep for bigjoiner atomic check
  2020-11-05 15:21   ` Ville Syrjälä
@ 2020-11-05 15:23     ` Ville Syrjälä
  2020-11-05 16:09       ` Navare, Manasi
  0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2020-11-05 15:23 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx

On Thu, Nov 05, 2020 at 05:21:31PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 02, 2020 at 01:19:05PM -0800, Manasi Navare wrote:
> > No functional changes here. Just pass intel_atomic_state
> > along with crtc_state to certain atomic_check functions.
> > This will lay the foundation for adding bigjoiner master/slave
> > states in atomic check.
> > 
> > v2:
> > * More prep with intel_atomic_state (Ville)
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_atomic.c  |  9 +++++----
> >  drivers/gpu/drm/i915/display/intel_atomic.h  |  3 ++-
> >  drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++--------
> >  3 files changed, 20 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> > index 86be032bcf96..e243ce97b534 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > @@ -270,14 +270,15 @@ void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
> >  	intel_crtc_put_color_blobs(crtc_state);
> >  }
> >  
> > -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
> > +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> > +				 const struct intel_crtc_state *from_crtc_state)
> >  {
> >  	drm_property_replace_blob(&crtc_state->hw.degamma_lut,
> > -				  crtc_state->uapi.degamma_lut);
> > +				  from_crtc_state->uapi.degamma_lut);
> >  	drm_property_replace_blob(&crtc_state->hw.gamma_lut,
> > -				  crtc_state->uapi.gamma_lut);
> > +				  from_crtc_state->uapi.gamma_lut);
> >  	drm_property_replace_blob(&crtc_state->hw.ctm,
> > -				  crtc_state->uapi.ctm);
> > +				  from_crtc_state->uapi.ctm);
> 
> This patch still seems to do two totally separate things:
> 1) pass intel_atomic_State all over (for which there was another
>    patch in the series as well?)

Looks like it was patch 4. So I would just squash all those changes from
here into patch 4.

> 2) this intel_crtc_copy_color_blobs() change
> 
> I would split these up because the commit message doesn't
> even mention the second change.
> 
> Each part looks fine on its own so with a proper split they are
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> >  }
> >  
> >  /**
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> > index 285de07011dc..62a3365ed5e6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> > @@ -43,7 +43,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
> >  void intel_crtc_destroy_state(struct drm_crtc *crtc,
> >  			       struct drm_crtc_state *state);
> >  void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
> > -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> > +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> > +				 const struct intel_crtc_state *from_crtc_state);
> >  struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> >  void intel_atomic_state_free(struct drm_atomic_state *state);
> >  void intel_atomic_state_clear(struct drm_atomic_state *state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 0bea90cdf242..ab10dfe705e4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -13459,13 +13459,17 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state)
> >  }
> >  
> >  static void
> > -intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
> > +intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
> > +					   struct intel_crtc_state *crtc_state)
> >  {
> > -	intel_crtc_copy_color_blobs(crtc_state);
> > +	const struct intel_crtc_state *from_crtc_state = crtc_state;
> > +
> > +	intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
> >  }
> >  
> >  static void
> > -intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
> > +intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
> > +				 struct intel_crtc_state *crtc_state)
> >  {
> >  	crtc_state->hw.enable = crtc_state->uapi.enable;
> >  	crtc_state->hw.active = crtc_state->uapi.active;
> > @@ -13473,7 +13477,7 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
> >  	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
> >  	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
> >  
> > -	intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
> > +	intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
> >  }
> >  
> >  static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> > @@ -13496,7 +13500,8 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
> >  }
> >  
> >  static int
> > -intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
> > +intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
> > +				 struct intel_crtc_state *crtc_state)
> >  {
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > @@ -13528,7 +13533,7 @@ intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
> >  	memcpy(crtc_state, saved_state, sizeof(*crtc_state));
> >  	kfree(saved_state);
> >  
> > -	intel_crtc_copy_uapi_to_hw_state(crtc_state);
> > +	intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
> >  
> >  	return 0;
> >  }
> > @@ -15233,12 +15238,12 @@ static int intel_atomic_check(struct drm_device *dev,
> >  					    new_crtc_state, i) {
> >  		if (!needs_modeset(new_crtc_state)) {
> >  			/* Light copy */
> > -			intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
> > +			intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state);
> >  
> >  			continue;
> >  		}
> >  
> > -		ret = intel_crtc_prepare_cleared_state(new_crtc_state);
> > +		ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
> >  		if (ret)
> >  			goto fail;
> >  
> > -- 
> > 2.19.1
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel
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^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [Intel-gfx] [PATCH v5 5/6] drm/i915/dp: Prep for bigjoiner atomic check
  2020-11-05 15:23     ` Ville Syrjälä
@ 2020-11-05 16:09       ` Navare, Manasi
  2020-11-05 16:16         ` Ville Syrjälä
  0 siblings, 1 reply; 32+ messages in thread
From: Navare, Manasi @ 2020-11-05 16:09 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Thu, Nov 05, 2020 at 05:23:33PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 05, 2020 at 05:21:31PM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 02, 2020 at 01:19:05PM -0800, Manasi Navare wrote:
> > > No functional changes here. Just pass intel_atomic_state
> > > along with crtc_state to certain atomic_check functions.
> > > This will lay the foundation for adding bigjoiner master/slave
> > > states in atomic check.
> > > 
> > > v2:
> > > * More prep with intel_atomic_state (Ville)
> > > 
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_atomic.c  |  9 +++++----
> > >  drivers/gpu/drm/i915/display/intel_atomic.h  |  3 ++-
> > >  drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++--------
> > >  3 files changed, 20 insertions(+), 13 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > index 86be032bcf96..e243ce97b534 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > @@ -270,14 +270,15 @@ void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
> > >  	intel_crtc_put_color_blobs(crtc_state);
> > >  }
> > >  
> > > -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
> > > +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> > > +				 const struct intel_crtc_state *from_crtc_state)
> > >  {
> > >  	drm_property_replace_blob(&crtc_state->hw.degamma_lut,
> > > -				  crtc_state->uapi.degamma_lut);
> > > +				  from_crtc_state->uapi.degamma_lut);
> > >  	drm_property_replace_blob(&crtc_state->hw.gamma_lut,
> > > -				  crtc_state->uapi.gamma_lut);
> > > +				  from_crtc_state->uapi.gamma_lut);
> > >  	drm_property_replace_blob(&crtc_state->hw.ctm,
> > > -				  crtc_state->uapi.ctm);
> > > +				  from_crtc_state->uapi.ctm);
> > 
> > This patch still seems to do two totally separate things:
> > 1) pass intel_atomic_State all over (for which there was another
> >    patch in the series as well?)
> 
> Looks like it was patch 4. So I would just squash all those changes from
> here into patch 4.

Okay so all the changes where I am sending the intel_atomic_state to functions
move those to Patch 4 and then just keep the
color blobs change here?

Manasi

> 
> > 2) this intel_crtc_copy_color_blobs() change
> > 
> > I would split these up because the commit message doesn't
> > even mention the second change.
> > 
> > Each part looks fine on its own so with a proper split they are
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > >  }
> > >  
> > >  /**
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> > > index 285de07011dc..62a3365ed5e6 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> > > @@ -43,7 +43,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
> > >  void intel_crtc_destroy_state(struct drm_crtc *crtc,
> > >  			       struct drm_crtc_state *state);
> > >  void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
> > > -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> > > +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> > > +				 const struct intel_crtc_state *from_crtc_state);
> > >  struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> > >  void intel_atomic_state_free(struct drm_atomic_state *state);
> > >  void intel_atomic_state_clear(struct drm_atomic_state *state);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 0bea90cdf242..ab10dfe705e4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -13459,13 +13459,17 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state)
> > >  }
> > >  
> > >  static void
> > > -intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
> > > +intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
> > > +					   struct intel_crtc_state *crtc_state)
> > >  {
> > > -	intel_crtc_copy_color_blobs(crtc_state);
> > > +	const struct intel_crtc_state *from_crtc_state = crtc_state;
> > > +
> > > +	intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
> > >  }
> > >  
> > >  static void
> > > -intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
> > > +intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
> > > +				 struct intel_crtc_state *crtc_state)
> > >  {
> > >  	crtc_state->hw.enable = crtc_state->uapi.enable;
> > >  	crtc_state->hw.active = crtc_state->uapi.active;
> > > @@ -13473,7 +13477,7 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
> > >  	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
> > >  	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
> > >  
> > > -	intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
> > > +	intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
> > >  }
> > >  
> > >  static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> > > @@ -13496,7 +13500,8 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
> > >  }
> > >  
> > >  static int
> > > -intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
> > > +intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
> > > +				 struct intel_crtc_state *crtc_state)
> > >  {
> > >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > @@ -13528,7 +13533,7 @@ intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
> > >  	memcpy(crtc_state, saved_state, sizeof(*crtc_state));
> > >  	kfree(saved_state);
> > >  
> > > -	intel_crtc_copy_uapi_to_hw_state(crtc_state);
> > > +	intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
> > >  
> > >  	return 0;
> > >  }
> > > @@ -15233,12 +15238,12 @@ static int intel_atomic_check(struct drm_device *dev,
> > >  					    new_crtc_state, i) {
> > >  		if (!needs_modeset(new_crtc_state)) {
> > >  			/* Light copy */
> > > -			intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
> > > +			intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state);
> > >  
> > >  			continue;
> > >  		}
> > >  
> > > -		ret = intel_crtc_prepare_cleared_state(new_crtc_state);
> > > +		ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
> > >  		if (ret)
> > >  			goto fail;
> > >  
> > > -- 
> > > 2.19.1
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> 
> -- 
> Ville Syrjälä
> Intel
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [Intel-gfx] [PATCH v5 5/6] drm/i915/dp: Prep for bigjoiner atomic check
  2020-11-05 16:09       ` Navare, Manasi
@ 2020-11-05 16:16         ` Ville Syrjälä
  0 siblings, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2020-11-05 16:16 UTC (permalink / raw)
  To: Navare, Manasi; +Cc: intel-gfx

On Thu, Nov 05, 2020 at 08:09:38AM -0800, Navare, Manasi wrote:
> On Thu, Nov 05, 2020 at 05:23:33PM +0200, Ville Syrjälä wrote:
> > On Thu, Nov 05, 2020 at 05:21:31PM +0200, Ville Syrjälä wrote:
> > > On Mon, Nov 02, 2020 at 01:19:05PM -0800, Manasi Navare wrote:
> > > > No functional changes here. Just pass intel_atomic_state
> > > > along with crtc_state to certain atomic_check functions.
> > > > This will lay the foundation for adding bigjoiner master/slave
> > > > states in atomic check.
> > > > 
> > > > v2:
> > > > * More prep with intel_atomic_state (Ville)
> > > > 
> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_atomic.c  |  9 +++++----
> > > >  drivers/gpu/drm/i915/display/intel_atomic.h  |  3 ++-
> > > >  drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++--------
> > > >  3 files changed, 20 insertions(+), 13 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > index 86be032bcf96..e243ce97b534 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > @@ -270,14 +270,15 @@ void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
> > > >  	intel_crtc_put_color_blobs(crtc_state);
> > > >  }
> > > >  
> > > > -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
> > > > +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> > > > +				 const struct intel_crtc_state *from_crtc_state)
> > > >  {
> > > >  	drm_property_replace_blob(&crtc_state->hw.degamma_lut,
> > > > -				  crtc_state->uapi.degamma_lut);
> > > > +				  from_crtc_state->uapi.degamma_lut);
> > > >  	drm_property_replace_blob(&crtc_state->hw.gamma_lut,
> > > > -				  crtc_state->uapi.gamma_lut);
> > > > +				  from_crtc_state->uapi.gamma_lut);
> > > >  	drm_property_replace_blob(&crtc_state->hw.ctm,
> > > > -				  crtc_state->uapi.ctm);
> > > > +				  from_crtc_state->uapi.ctm);
> > > 
> > > This patch still seems to do two totally separate things:
> > > 1) pass intel_atomic_State all over (for which there was another
> > >    patch in the series as well?)
> > 
> > Looks like it was patch 4. So I would just squash all those changes from
> > here into patch 4.
> 
> Okay so all the changes where I am sending the intel_atomic_state to functions
> move those to Patch 4 and then just keep the
> color blobs change here?

Yeah. Not entirely certain the color blob thing needs its own patch
anymore then, but no real harm in having it like that I guess.

> 
> Manasi
> 
> > 
> > > 2) this intel_crtc_copy_color_blobs() change
> > > 
> > > I would split these up because the commit message doesn't
> > > even mention the second change.
> > > 
> > > Each part looks fine on its own so with a proper split they are
> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > >  }
> > > >  
> > > >  /**
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> > > > index 285de07011dc..62a3365ed5e6 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> > > > @@ -43,7 +43,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
> > > >  void intel_crtc_destroy_state(struct drm_crtc *crtc,
> > > >  			       struct drm_crtc_state *state);
> > > >  void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
> > > > -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> > > > +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
> > > > +				 const struct intel_crtc_state *from_crtc_state);
> > > >  struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> > > >  void intel_atomic_state_free(struct drm_atomic_state *state);
> > > >  void intel_atomic_state_clear(struct drm_atomic_state *state);
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 0bea90cdf242..ab10dfe705e4 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -13459,13 +13459,17 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state)
> > > >  }
> > > >  
> > > >  static void
> > > > -intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
> > > > +intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
> > > > +					   struct intel_crtc_state *crtc_state)
> > > >  {
> > > > -	intel_crtc_copy_color_blobs(crtc_state);
> > > > +	const struct intel_crtc_state *from_crtc_state = crtc_state;
> > > > +
> > > > +	intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
> > > >  }
> > > >  
> > > >  static void
> > > > -intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
> > > > +intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
> > > > +				 struct intel_crtc_state *crtc_state)
> > > >  {
> > > >  	crtc_state->hw.enable = crtc_state->uapi.enable;
> > > >  	crtc_state->hw.active = crtc_state->uapi.active;
> > > > @@ -13473,7 +13477,7 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
> > > >  	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
> > > >  	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
> > > >  
> > > > -	intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
> > > > +	intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
> > > >  }
> > > >  
> > > >  static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> > > > @@ -13496,7 +13500,8 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
> > > >  }
> > > >  
> > > >  static int
> > > > -intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
> > > > +intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
> > > > +				 struct intel_crtc_state *crtc_state)
> > > >  {
> > > >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > > @@ -13528,7 +13533,7 @@ intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
> > > >  	memcpy(crtc_state, saved_state, sizeof(*crtc_state));
> > > >  	kfree(saved_state);
> > > >  
> > > > -	intel_crtc_copy_uapi_to_hw_state(crtc_state);
> > > > +	intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
> > > >  
> > > >  	return 0;
> > > >  }
> > > > @@ -15233,12 +15238,12 @@ static int intel_atomic_check(struct drm_device *dev,
> > > >  					    new_crtc_state, i) {
> > > >  		if (!needs_modeset(new_crtc_state)) {
> > > >  			/* Light copy */
> > > > -			intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
> > > > +			intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state);
> > > >  
> > > >  			continue;
> > > >  		}
> > > >  
> > > > -		ret = intel_crtc_prepare_cleared_state(new_crtc_state);
> > > > +		ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
> > > >  		if (ret)
> > > >  			goto fail;
> > > >  
> > > > -- 
> > > > 2.19.1
> > > 
> > > -- 
> > > Ville Syrjälä
> > > Intel
> > 
> > -- 
> > Ville Syrjälä
> > Intel

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] [PATCH v5 6/6] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
                   ` (3 preceding siblings ...)
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 5/6] drm/i915/dp: Prep for bigjoiner atomic check Manasi Navare
@ 2020-11-02 21:19 ` Manasi Navare
  2020-11-03 16:00   ` [Intel-gfx] [PATCH v6 " Manasi Navare
  2020-11-02 21:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Patchwork
                   ` (10 subsequent siblings)
  15 siblings, 1 reply; 32+ messages in thread
From: Manasi Navare @ 2020-11-02 21:19 UTC (permalink / raw)
  To: intel-gfx

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.

v12:
* slice_count logic simplify (Ville)
* Fix unnecessary changes in downstream_mode_valid (Ville)
v11:
* Make intel_dp_can_bigjoiner non static
so it can be used in intel_display (Manasi)
v10:
* Simplify logic (Ville)
* Allow bigjoiner on edp (Ville)
v9:
* Restric Bigjoiner on PORT A (Ville)
v8:
* use source dotclock for max dotclock (Manasi)
v7:
* Add can_bigjoiner() helper (Ville)
* Pass bigjoiner to plane_size validation (Ville)
v6:
* Rebase after dp_downstream mode valid changes (Manasi)
v5:
* Increase max plane width to support 8K with bigjoiner (Maarten)
v4:
* Rebase (Manasi)

Changes since v1:
- Disallow bigjoiner on eDP.
Changes since v2:
- Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
  and split off the downstream and source checking to its own function.
  (Ville)
v3:
* Rebase (Manasi)

Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  5 +-
 drivers/gpu/drm/i915/display/intel_display.h |  3 +-
 drivers/gpu/drm/i915/display/intel_dp.c      | 77 ++++++++++++++++----
 drivers/gpu/drm/i915/display/intel_dp.h      |  1 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_dsi.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c    |  2 +-
 7 files changed, 72 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ab10dfe705e4..1ebbac253c36 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17777,7 +17777,8 @@ intel_mode_valid(struct drm_device *dev,
 
 enum drm_mode_status
 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
-				const struct drm_display_mode *mode)
+				const struct drm_display_mode *mode,
+				bool bigjoiner)
 {
 	int plane_width_max, plane_height_max;
 
@@ -17794,7 +17795,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
 	 * too big for that.
 	 */
 	if (INTEL_GEN(dev_priv) >= 11) {
-		plane_width_max = 5120;
+		plane_width_max = 5120 << bigjoiner;
 		plane_height_max = 4320;
 	} else {
 		plane_width_max = 5120;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index be774f216065..d24077df1711 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -513,7 +513,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
 enum drm_mode_status
 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
-				const struct drm_display_mode *mode);
+				const struct drm_display_mode *mode,
+				bool bigjoiner);
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ca4d4a8122d9..fb5d5a36f606 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -254,6 +254,17 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 	return max_link_clock * max_lanes;
 }
 
+bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct intel_encoder *encoder = &intel_dig_port->base;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	return INTEL_GEN(dev_priv) >= 12 ||
+		(INTEL_GEN(dev_priv) == 11 &&
+		 encoder->port != PORT_A);
+}
+
 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -519,7 +530,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
 
 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 				       u32 link_clock, u32 lane_count,
-				       u32 mode_clock, u32 mode_hdisplay)
+				       u32 mode_clock, u32 mode_hdisplay,
+				       bool bigjoiner)
 {
 	u32 bits_per_pixel, max_bpp_small_joiner_ram;
 	int i;
@@ -537,6 +549,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 	/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 	max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 		mode_hdisplay;
+
+	if (bigjoiner)
+		max_bpp_small_joiner_ram *= 2;
+
 	drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 		    max_bpp_small_joiner_ram);
 
@@ -546,6 +562,15 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 	 */
 	bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 
+	if (bigjoiner) {
+		u32 max_bpp_bigjoiner =
+			i915->max_cdclk_freq * 48 /
+			intel_dp_mode_to_fec_clock(mode_clock);
+
+		DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
+		bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
+	}
+
 	/* Error out if the max bpp is less than smallest allowed valid bpp */
 	if (bits_per_pixel < valid_dsc_bpp[0]) {
 		drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
@@ -568,7 +593,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 }
 
 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
-				       int mode_clock, int mode_hdisplay)
+				       int mode_clock, int mode_hdisplay,
+				       bool bigjoiner)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	u8 min_slice_count, i;
@@ -595,12 +621,18 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 
 	/* Find the closest match to the valid slice count values */
 	for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
-		if (valid_dsc_slicecount[i] >
-		    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
-						    false))
+		u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
+
+		if (test_slice_count >
+		    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 			break;
-		if (min_slice_count  <= valid_dsc_slicecount[i])
-			return valid_dsc_slicecount[i];
+
+		/* big joiner needs small joiner to be enabled */
+		if (bigjoiner && test_slice_count < 4)
+			continue;
+
+		if (min_slice_count <= test_slice_count)
+			return test_slice_count;
 	}
 
 	drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
@@ -717,6 +749,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	u16 dsc_max_output_bpp = 0;
 	u8 dsc_slice_count = 0;
 	enum drm_mode_status status;
+	bool dsc = false, bigjoiner = false;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
@@ -737,6 +770,13 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	if (mode->clock < 10000)
 		return MODE_CLOCK_LOW;
 
+	if (target_clock > max_dotclk && intel_dp_can_bigjoiner(intel_dp)) {
+		bigjoiner = true;
+		max_dotclk *= 2;
+	}
+	if (target_clock > max_dotclk)
+		return MODE_CLOCK_HIGH;
+
 	max_link_clock = intel_dp_max_link_rate(intel_dp);
 	max_lanes = intel_dp_max_lane_count(intel_dp);
 
@@ -765,16 +805,23 @@ intel_dp_mode_valid(struct drm_connector *connector,
 							    max_link_clock,
 							    max_lanes,
 							    target_clock,
-							    mode->hdisplay) >> 4;
+							    mode->hdisplay,
+							    bigjoiner) >> 4;
 			dsc_slice_count =
 				intel_dp_dsc_get_slice_count(intel_dp,
 							     target_clock,
-							     mode->hdisplay);
+							     mode->hdisplay,
+							     bigjoiner);
 		}
+
+		dsc = dsc_max_output_bpp && dsc_slice_count;
 	}
 
-	if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
-	    target_clock > max_dotclk)
+	/* big joiner configuration needs DSC */
+	if (bigjoiner && !dsc)
+		return MODE_CLOCK_HIGH;
+
+	if (mode_rate > max_rate && !dsc)
 		return MODE_CLOCK_HIGH;
 
 	status = intel_dp_mode_valid_downstream(intel_connector,
@@ -782,7 +829,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	if (status != MODE_OK)
 		return status;
 
-	return intel_mode_valid_max_plane_size(dev_priv, mode);
+	return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
 }
 
 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
@@ -2351,11 +2398,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 						    pipe_config->port_clock,
 						    pipe_config->lane_count,
 						    adjusted_mode->crtc_clock,
-						    adjusted_mode->crtc_hdisplay);
+						    adjusted_mode->crtc_hdisplay,
+						    false);
 		dsc_dp_slice_count =
 			intel_dp_dsc_get_slice_count(intel_dp,
 						     adjusted_mode->crtc_clock,
-						     adjusted_mode->crtc_hdisplay);
+						     adjusted_mode->crtc_hdisplay,
+						     false);
 		if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
 			drm_dbg_kms(&dev_priv->drm,
 				    "Compressed BPP/Slice Count not supported\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 3f862b4fd34f..b871a09b6901 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -106,6 +106,7 @@ bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
 int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
+bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp);
 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
 			    const struct drm_connector_state *conn_state);
 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index c8fcec4d0788..0c8684634fca 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -714,7 +714,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
 		return 0;
 	}
 
-	*status = intel_mode_valid_max_plane_size(dev_priv, mode);
+	*status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
index afa4e6817e8c..f453ceb8d149 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi.c
@@ -75,7 +75,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
 			return MODE_CLOCK_HIGH;
 	}
 
-	return intel_mode_valid_max_plane_size(dev_priv, mode);
+	return intel_mode_valid_max_plane_size(dev_priv, mode, false);
 }
 
 struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f90838bc74fb..82674a8853c6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2274,7 +2274,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
 	if (status != MODE_OK)
 		return status;
 
-	return intel_mode_valid_max_plane_size(dev_priv, mode);
+	return intel_mode_valid_max_plane_size(dev_priv, mode, false);
 }
 
 bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related	[flat|nested] 32+ messages in thread

* [Intel-gfx] [PATCH v6 6/6] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 6/6] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3 Manasi Navare
@ 2020-11-03 16:00   ` Manasi Navare
  2020-11-05 16:11     ` Navare, Manasi
  2020-11-05 16:27     ` Ville Syrjälä
  0 siblings, 2 replies; 32+ messages in thread
From: Manasi Navare @ 2020-11-03 16:00 UTC (permalink / raw)
  To: intel-gfx

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.

v13:
* Allow bigjoiner if hdisplay >5120
v12:
* slice_count logic simplify (Ville)
* Fix unnecessary changes in downstream_mode_valid (Ville)
v11:
* Make intel_dp_can_bigjoiner non static
so it can be used in intel_display (Manasi)
v10:
* Simplify logic (Ville)
* Allow bigjoiner on edp (Ville)
v9:
* Restric Bigjoiner on PORT A (Ville)
v8:
* use source dotclock for max dotclock (Manasi)
v7:
* Add can_bigjoiner() helper (Ville)
* Pass bigjoiner to plane_size validation (Ville)
v6:
* Rebase after dp_downstream mode valid changes (Manasi)
v5:
* Increase max plane width to support 8K with bigjoiner (Maarten)
v4:
* Rebase (Manasi)

Changes since v1:
- Disallow bigjoiner on eDP.
Changes since v2:
- Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
  and split off the downstream and source checking to its own function.
  (Ville)
v3:
* Rebase (Manasi)

Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  5 +-
 drivers/gpu/drm/i915/display/intel_display.h |  3 +-
 drivers/gpu/drm/i915/display/intel_dp.c      | 78 ++++++++++++++++----
 drivers/gpu/drm/i915/display/intel_dp.h      |  1 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_dsi.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c    |  2 +-
 7 files changed, 73 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c59d9c2bd473..73bd9721c1a8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17779,7 +17779,8 @@ intel_mode_valid(struct drm_device *dev,
 
 enum drm_mode_status
 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
-				const struct drm_display_mode *mode)
+				const struct drm_display_mode *mode,
+				bool bigjoiner)
 {
 	int plane_width_max, plane_height_max;
 
@@ -17796,7 +17797,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
 	 * too big for that.
 	 */
 	if (INTEL_GEN(dev_priv) >= 11) {
-		plane_width_max = 5120;
+		plane_width_max = 5120 << bigjoiner;
 		plane_height_max = 4320;
 	} else {
 		plane_width_max = 5120;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index be774f216065..d24077df1711 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -513,7 +513,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
 enum drm_mode_status
 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
-				const struct drm_display_mode *mode);
+				const struct drm_display_mode *mode,
+				bool bigjoiner);
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ca4d4a8122d9..d2023fc54a18 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -254,6 +254,17 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 	return max_link_clock * max_lanes;
 }
 
+bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct intel_encoder *encoder = &intel_dig_port->base;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	return INTEL_GEN(dev_priv) >= 12 ||
+		(INTEL_GEN(dev_priv) == 11 &&
+		 encoder->port != PORT_A);
+}
+
 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -519,7 +530,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
 
 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 				       u32 link_clock, u32 lane_count,
-				       u32 mode_clock, u32 mode_hdisplay)
+				       u32 mode_clock, u32 mode_hdisplay,
+				       bool bigjoiner)
 {
 	u32 bits_per_pixel, max_bpp_small_joiner_ram;
 	int i;
@@ -537,6 +549,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 	/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 	max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 		mode_hdisplay;
+
+	if (bigjoiner)
+		max_bpp_small_joiner_ram *= 2;
+
 	drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 		    max_bpp_small_joiner_ram);
 
@@ -546,6 +562,15 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 	 */
 	bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 
+	if (bigjoiner) {
+		u32 max_bpp_bigjoiner =
+			i915->max_cdclk_freq * 48 /
+			intel_dp_mode_to_fec_clock(mode_clock);
+
+		DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
+		bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
+	}
+
 	/* Error out if the max bpp is less than smallest allowed valid bpp */
 	if (bits_per_pixel < valid_dsc_bpp[0]) {
 		drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
@@ -568,7 +593,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 }
 
 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
-				       int mode_clock, int mode_hdisplay)
+				       int mode_clock, int mode_hdisplay,
+				       bool bigjoiner)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	u8 min_slice_count, i;
@@ -595,12 +621,18 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 
 	/* Find the closest match to the valid slice count values */
 	for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
-		if (valid_dsc_slicecount[i] >
-		    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
-						    false))
+		u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
+
+		if (test_slice_count >
+		    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 			break;
-		if (min_slice_count  <= valid_dsc_slicecount[i])
-			return valid_dsc_slicecount[i];
+
+		/* big joiner needs small joiner to be enabled */
+		if (bigjoiner && test_slice_count < 4)
+			continue;
+
+		if (min_slice_count <= test_slice_count)
+			return test_slice_count;
 	}
 
 	drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
@@ -717,6 +749,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	u16 dsc_max_output_bpp = 0;
 	u8 dsc_slice_count = 0;
 	enum drm_mode_status status;
+	bool dsc = false, bigjoiner = false;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return MODE_NO_DBLESCAN;
@@ -737,6 +770,14 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	if (mode->clock < 10000)
 		return MODE_CLOCK_LOW;
 
+	if ((target_clock > max_dotclk || mode->hdisplay > 5120)
+	    && intel_dp_can_bigjoiner(intel_dp)) {
+		bigjoiner = true;
+		max_dotclk *= 2;
+	}
+	if (target_clock > max_dotclk)
+		return MODE_CLOCK_HIGH;
+
 	max_link_clock = intel_dp_max_link_rate(intel_dp);
 	max_lanes = intel_dp_max_lane_count(intel_dp);
 
@@ -765,16 +806,23 @@ intel_dp_mode_valid(struct drm_connector *connector,
 							    max_link_clock,
 							    max_lanes,
 							    target_clock,
-							    mode->hdisplay) >> 4;
+							    mode->hdisplay,
+							    bigjoiner) >> 4;
 			dsc_slice_count =
 				intel_dp_dsc_get_slice_count(intel_dp,
 							     target_clock,
-							     mode->hdisplay);
+							     mode->hdisplay,
+							     bigjoiner);
 		}
+
+		dsc = dsc_max_output_bpp && dsc_slice_count;
 	}
 
-	if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
-	    target_clock > max_dotclk)
+	/* big joiner configuration needs DSC */
+	if (bigjoiner && !dsc)
+		return MODE_CLOCK_HIGH;
+
+	if (mode_rate > max_rate && !dsc)
 		return MODE_CLOCK_HIGH;
 
 	status = intel_dp_mode_valid_downstream(intel_connector,
@@ -782,7 +830,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	if (status != MODE_OK)
 		return status;
 
-	return intel_mode_valid_max_plane_size(dev_priv, mode);
+	return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
 }
 
 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
@@ -2351,11 +2399,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 						    pipe_config->port_clock,
 						    pipe_config->lane_count,
 						    adjusted_mode->crtc_clock,
-						    adjusted_mode->crtc_hdisplay);
+						    adjusted_mode->crtc_hdisplay,
+						    false);
 		dsc_dp_slice_count =
 			intel_dp_dsc_get_slice_count(intel_dp,
 						     adjusted_mode->crtc_clock,
-						     adjusted_mode->crtc_hdisplay);
+						     adjusted_mode->crtc_hdisplay,
+						     false);
 		if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
 			drm_dbg_kms(&dev_priv->drm,
 				    "Compressed BPP/Slice Count not supported\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 3f862b4fd34f..b871a09b6901 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -106,6 +106,7 @@ bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
 int intel_dp_link_required(int pixel_clock, int bpp);
 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
+bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp);
 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
 			    const struct drm_connector_state *conn_state);
 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index c8fcec4d0788..0c8684634fca 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -714,7 +714,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
 		return 0;
 	}
 
-	*status = intel_mode_valid_max_plane_size(dev_priv, mode);
+	*status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
index afa4e6817e8c..f453ceb8d149 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi.c
@@ -75,7 +75,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
 			return MODE_CLOCK_HIGH;
 	}
 
-	return intel_mode_valid_max_plane_size(dev_priv, mode);
+	return intel_mode_valid_max_plane_size(dev_priv, mode, false);
 }
 
 struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f90838bc74fb..82674a8853c6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2274,7 +2274,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
 	if (status != MODE_OK)
 		return status;
 
-	return intel_mode_valid_max_plane_size(dev_priv, mode);
+	return intel_mode_valid_max_plane_size(dev_priv, mode, false);
 }
 
 bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread

* Re: [Intel-gfx] [PATCH v6 6/6] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
  2020-11-03 16:00   ` [Intel-gfx] [PATCH v6 " Manasi Navare
@ 2020-11-05 16:11     ` Navare, Manasi
  2020-11-05 16:27     ` Ville Syrjälä
  1 sibling, 0 replies; 32+ messages in thread
From: Navare, Manasi @ 2020-11-05 16:11 UTC (permalink / raw)
  To: intel-gfx

@Ville, any feedback on this patch here?
Or should this be usptreamed as part of the core series
since this actually allows the 8K modes

Manasi


On Tue, Nov 03, 2020 at 08:00:40AM -0800, Manasi Navare wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> 
> Small changes to intel_dp_mode_valid(), allow listing modes that
> can only be supported in the bigjoiner configuration, which is
> not supported yet.
> 
> v13:
> * Allow bigjoiner if hdisplay >5120
> v12:
> * slice_count logic simplify (Ville)
> * Fix unnecessary changes in downstream_mode_valid (Ville)
> v11:
> * Make intel_dp_can_bigjoiner non static
> so it can be used in intel_display (Manasi)
> v10:
> * Simplify logic (Ville)
> * Allow bigjoiner on edp (Ville)
> v9:
> * Restric Bigjoiner on PORT A (Ville)
> v8:
> * use source dotclock for max dotclock (Manasi)
> v7:
> * Add can_bigjoiner() helper (Ville)
> * Pass bigjoiner to plane_size validation (Ville)
> v6:
> * Rebase after dp_downstream mode valid changes (Manasi)
> v5:
> * Increase max plane width to support 8K with bigjoiner (Maarten)
> v4:
> * Rebase (Manasi)
> 
> Changes since v1:
> - Disallow bigjoiner on eDP.
> Changes since v2:
> - Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
>   and split off the downstream and source checking to its own function.
>   (Ville)
> v3:
> * Rebase (Manasi)
> 
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  5 +-
>  drivers/gpu/drm/i915/display/intel_display.h |  3 +-
>  drivers/gpu/drm/i915/display/intel_dp.c      | 78 ++++++++++++++++----
>  drivers/gpu/drm/i915/display/intel_dp.h      |  1 +
>  drivers/gpu/drm/i915/display/intel_dp_mst.c  |  2 +-
>  drivers/gpu/drm/i915/display/intel_dsi.c     |  2 +-
>  drivers/gpu/drm/i915/display/intel_hdmi.c    |  2 +-
>  7 files changed, 73 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c59d9c2bd473..73bd9721c1a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17779,7 +17779,8 @@ intel_mode_valid(struct drm_device *dev,
>  
>  enum drm_mode_status
>  intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> -				const struct drm_display_mode *mode)
> +				const struct drm_display_mode *mode,
> +				bool bigjoiner)
>  {
>  	int plane_width_max, plane_height_max;
>  
> @@ -17796,7 +17797,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
>  	 * too big for that.
>  	 */
>  	if (INTEL_GEN(dev_priv) >= 11) {
> -		plane_width_max = 5120;
> +		plane_width_max = 5120 << bigjoiner;
>  		plane_height_max = 4320;
>  	} else {
>  		plane_width_max = 5120;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index be774f216065..d24077df1711 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -513,7 +513,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>  bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
>  enum drm_mode_status
>  intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> -				const struct drm_display_mode *mode);
> +				const struct drm_display_mode *mode,
> +				bool bigjoiner);
>  enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
>  bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index ca4d4a8122d9..d2023fc54a18 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -254,6 +254,17 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
>  	return max_link_clock * max_lanes;
>  }
>  
> +bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct intel_encoder *encoder = &intel_dig_port->base;
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> +	return INTEL_GEN(dev_priv) >= 12 ||
> +		(INTEL_GEN(dev_priv) == 11 &&
> +		 encoder->port != PORT_A);
> +}
> +
>  static int cnl_max_source_rate(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> @@ -519,7 +530,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
>  
>  static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
>  				       u32 link_clock, u32 lane_count,
> -				       u32 mode_clock, u32 mode_hdisplay)
> +				       u32 mode_clock, u32 mode_hdisplay,
> +				       bool bigjoiner)
>  {
>  	u32 bits_per_pixel, max_bpp_small_joiner_ram;
>  	int i;
> @@ -537,6 +549,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
>  	/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
>  	max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
>  		mode_hdisplay;
> +
> +	if (bigjoiner)
> +		max_bpp_small_joiner_ram *= 2;
> +
>  	drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
>  		    max_bpp_small_joiner_ram);
>  
> @@ -546,6 +562,15 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
>  	 */
>  	bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
>  
> +	if (bigjoiner) {
> +		u32 max_bpp_bigjoiner =
> +			i915->max_cdclk_freq * 48 /
> +			intel_dp_mode_to_fec_clock(mode_clock);
> +
> +		DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
> +		bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
> +	}
> +
>  	/* Error out if the max bpp is less than smallest allowed valid bpp */
>  	if (bits_per_pixel < valid_dsc_bpp[0]) {
>  		drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
> @@ -568,7 +593,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
>  }
>  
>  static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> -				       int mode_clock, int mode_hdisplay)
> +				       int mode_clock, int mode_hdisplay,
> +				       bool bigjoiner)
>  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>  	u8 min_slice_count, i;
> @@ -595,12 +621,18 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
>  
>  	/* Find the closest match to the valid slice count values */
>  	for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
> -		if (valid_dsc_slicecount[i] >
> -		    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
> -						    false))
> +		u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
> +
> +		if (test_slice_count >
> +		    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
>  			break;
> -		if (min_slice_count  <= valid_dsc_slicecount[i])
> -			return valid_dsc_slicecount[i];
> +
> +		/* big joiner needs small joiner to be enabled */
> +		if (bigjoiner && test_slice_count < 4)
> +			continue;
> +
> +		if (min_slice_count <= test_slice_count)
> +			return test_slice_count;
>  	}
>  
>  	drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
> @@ -717,6 +749,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  	u16 dsc_max_output_bpp = 0;
>  	u8 dsc_slice_count = 0;
>  	enum drm_mode_status status;
> +	bool dsc = false, bigjoiner = false;
>  
>  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
>  		return MODE_NO_DBLESCAN;
> @@ -737,6 +770,14 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  	if (mode->clock < 10000)
>  		return MODE_CLOCK_LOW;
>  
> +	if ((target_clock > max_dotclk || mode->hdisplay > 5120)
> +	    && intel_dp_can_bigjoiner(intel_dp)) {
> +		bigjoiner = true;
> +		max_dotclk *= 2;
> +	}
> +	if (target_clock > max_dotclk)
> +		return MODE_CLOCK_HIGH;
> +
>  	max_link_clock = intel_dp_max_link_rate(intel_dp);
>  	max_lanes = intel_dp_max_lane_count(intel_dp);
>  
> @@ -765,16 +806,23 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  							    max_link_clock,
>  							    max_lanes,
>  							    target_clock,
> -							    mode->hdisplay) >> 4;
> +							    mode->hdisplay,
> +							    bigjoiner) >> 4;
>  			dsc_slice_count =
>  				intel_dp_dsc_get_slice_count(intel_dp,
>  							     target_clock,
> -							     mode->hdisplay);
> +							     mode->hdisplay,
> +							     bigjoiner);
>  		}
> +
> +		dsc = dsc_max_output_bpp && dsc_slice_count;
>  	}
>  
> -	if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
> -	    target_clock > max_dotclk)
> +	/* big joiner configuration needs DSC */
> +	if (bigjoiner && !dsc)
> +		return MODE_CLOCK_HIGH;
> +
> +	if (mode_rate > max_rate && !dsc)
>  		return MODE_CLOCK_HIGH;
>  
>  	status = intel_dp_mode_valid_downstream(intel_connector,
> @@ -782,7 +830,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  	if (status != MODE_OK)
>  		return status;
>  
> -	return intel_mode_valid_max_plane_size(dev_priv, mode);
> +	return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
>  }
>  
>  u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
> @@ -2351,11 +2399,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  						    pipe_config->port_clock,
>  						    pipe_config->lane_count,
>  						    adjusted_mode->crtc_clock,
> -						    adjusted_mode->crtc_hdisplay);
> +						    adjusted_mode->crtc_hdisplay,
> +						    false);
>  		dsc_dp_slice_count =
>  			intel_dp_dsc_get_slice_count(intel_dp,
>  						     adjusted_mode->crtc_clock,
> -						     adjusted_mode->crtc_hdisplay);
> +						     adjusted_mode->crtc_hdisplay,
> +						     false);
>  		if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
>  			drm_dbg_kms(&dev_priv->drm,
>  				    "Compressed BPP/Slice Count not supported\n");
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 3f862b4fd34f..b871a09b6901 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -106,6 +106,7 @@ bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
>  bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
>  int intel_dp_link_required(int pixel_clock, int bpp);
>  int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
> +bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp);
>  bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
>  			    const struct drm_connector_state *conn_state);
>  void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index c8fcec4d0788..0c8684634fca 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -714,7 +714,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
>  		return 0;
>  	}
>  
> -	*status = intel_mode_valid_max_plane_size(dev_priv, mode);
> +	*status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
> index afa4e6817e8c..f453ceb8d149 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsi.c
> @@ -75,7 +75,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
>  			return MODE_CLOCK_HIGH;
>  	}
>  
> -	return intel_mode_valid_max_plane_size(dev_priv, mode);
> +	return intel_mode_valid_max_plane_size(dev_priv, mode, false);
>  }
>  
>  struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index f90838bc74fb..82674a8853c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2274,7 +2274,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
>  	if (status != MODE_OK)
>  		return status;
>  
> -	return intel_mode_valid_max_plane_size(dev_priv, mode);
> +	return intel_mode_valid_max_plane_size(dev_priv, mode, false);
>  }
>  
>  bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
> -- 
> 2.19.1
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [Intel-gfx] [PATCH v6 6/6] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
  2020-11-03 16:00   ` [Intel-gfx] [PATCH v6 " Manasi Navare
  2020-11-05 16:11     ` Navare, Manasi
@ 2020-11-05 16:27     ` Ville Syrjälä
  1 sibling, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2020-11-05 16:27 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx

On Tue, Nov 03, 2020 at 08:00:40AM -0800, Manasi Navare wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> 
> Small changes to intel_dp_mode_valid(), allow listing modes that
> can only be supported in the bigjoiner configuration, which is
> not supported yet.
> 
> v13:
> * Allow bigjoiner if hdisplay >5120
> v12:
> * slice_count logic simplify (Ville)
> * Fix unnecessary changes in downstream_mode_valid (Ville)
> v11:
> * Make intel_dp_can_bigjoiner non static
> so it can be used in intel_display (Manasi)
> v10:
> * Simplify logic (Ville)
> * Allow bigjoiner on edp (Ville)
> v9:
> * Restric Bigjoiner on PORT A (Ville)
> v8:
> * use source dotclock for max dotclock (Manasi)
> v7:
> * Add can_bigjoiner() helper (Ville)
> * Pass bigjoiner to plane_size validation (Ville)
> v6:
> * Rebase after dp_downstream mode valid changes (Manasi)
> v5:
> * Increase max plane width to support 8K with bigjoiner (Maarten)
> v4:
> * Rebase (Manasi)
> 
> Changes since v1:
> - Disallow bigjoiner on eDP.
> Changes since v2:
> - Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
>   and split off the downstream and source checking to its own function.
>   (Ville)
> v3:
> * Rebase (Manasi)
> 
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  5 +-
>  drivers/gpu/drm/i915/display/intel_display.h |  3 +-
>  drivers/gpu/drm/i915/display/intel_dp.c      | 78 ++++++++++++++++----
>  drivers/gpu/drm/i915/display/intel_dp.h      |  1 +
>  drivers/gpu/drm/i915/display/intel_dp_mst.c  |  2 +-
>  drivers/gpu/drm/i915/display/intel_dsi.c     |  2 +-
>  drivers/gpu/drm/i915/display/intel_hdmi.c    |  2 +-
>  7 files changed, 73 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c59d9c2bd473..73bd9721c1a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17779,7 +17779,8 @@ intel_mode_valid(struct drm_device *dev,
>  
>  enum drm_mode_status
>  intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> -				const struct drm_display_mode *mode)
> +				const struct drm_display_mode *mode,
> +				bool bigjoiner)
>  {
>  	int plane_width_max, plane_height_max;
>  
> @@ -17796,7 +17797,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
>  	 * too big for that.
>  	 */
>  	if (INTEL_GEN(dev_priv) >= 11) {
> -		plane_width_max = 5120;
> +		plane_width_max = 5120 << bigjoiner;
>  		plane_height_max = 4320;
>  	} else {
>  		plane_width_max = 5120;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index be774f216065..d24077df1711 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -513,7 +513,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>  bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
>  enum drm_mode_status
>  intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> -				const struct drm_display_mode *mode);
> +				const struct drm_display_mode *mode,
> +				bool bigjoiner);
>  enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
>  bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index ca4d4a8122d9..d2023fc54a18 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -254,6 +254,17 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
>  	return max_link_clock * max_lanes;
>  }
>  
> +bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct intel_encoder *encoder = &intel_dig_port->base;
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +

If we want to merge this before the rest of the bigjoiner series we're
gping to need to neuter this function. Otherwise we're going to start
accepting modes tht need the bigjoiner before we actually have bigjoiner
support.

So I'd say FIXME+return false here for now if we want to merge this.

> +	return INTEL_GEN(dev_priv) >= 12 ||
> +		(INTEL_GEN(dev_priv) == 11 &&
> +		 encoder->port != PORT_A);
> +}
> +
>  static int cnl_max_source_rate(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> @@ -519,7 +530,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
>  
>  static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
>  				       u32 link_clock, u32 lane_count,
> -				       u32 mode_clock, u32 mode_hdisplay)
> +				       u32 mode_clock, u32 mode_hdisplay,
> +				       bool bigjoiner)
>  {
>  	u32 bits_per_pixel, max_bpp_small_joiner_ram;
>  	int i;
> @@ -537,6 +549,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
>  	/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
>  	max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
>  		mode_hdisplay;
> +
> +	if (bigjoiner)
> +		max_bpp_small_joiner_ram *= 2;
> +
>  	drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
>  		    max_bpp_small_joiner_ram);
>  
> @@ -546,6 +562,15 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
>  	 */
>  	bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
>  
> +	if (bigjoiner) {
> +		u32 max_bpp_bigjoiner =
> +			i915->max_cdclk_freq * 48 /
> +			intel_dp_mode_to_fec_clock(mode_clock);
> +
> +		DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
> +		bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
> +	}
> +
>  	/* Error out if the max bpp is less than smallest allowed valid bpp */
>  	if (bits_per_pixel < valid_dsc_bpp[0]) {
>  		drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
> @@ -568,7 +593,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
>  }
>  
>  static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
> -				       int mode_clock, int mode_hdisplay)
> +				       int mode_clock, int mode_hdisplay,
> +				       bool bigjoiner)
>  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>  	u8 min_slice_count, i;
> @@ -595,12 +621,18 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
>  
>  	/* Find the closest match to the valid slice count values */
>  	for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
> -		if (valid_dsc_slicecount[i] >
> -		    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
> -						    false))
> +		u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
> +
> +		if (test_slice_count >
> +		    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
>  			break;
> -		if (min_slice_count  <= valid_dsc_slicecount[i])
> -			return valid_dsc_slicecount[i];
> +
> +		/* big joiner needs small joiner to be enabled */
> +		if (bigjoiner && test_slice_count < 4)
> +			continue;
> +
> +		if (min_slice_count <= test_slice_count)
> +			return test_slice_count;
>  	}
>  
>  	drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
> @@ -717,6 +749,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  	u16 dsc_max_output_bpp = 0;
>  	u8 dsc_slice_count = 0;
>  	enum drm_mode_status status;
> +	bool dsc = false, bigjoiner = false;
>  
>  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
>  		return MODE_NO_DBLESCAN;
> @@ -737,6 +770,14 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  	if (mode->clock < 10000)
>  		return MODE_CLOCK_LOW;
>  
> +	if ((target_clock > max_dotclk || mode->hdisplay > 5120)

Sad that we now have to duplicate the plane width limit here. But I have
no great ideas for it at the moment. Maybe one idea would be for
intel_mode_valid_max_plane_size() to take 'bool *bigjoiner' instead
and adjust as needed. Not sure. We're definitely going to have to do
something about this for future platforms where the plane width limit
might be different.

As stated, no idea about the dsc stuff, but otherwise this is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>


> +	    && intel_dp_can_bigjoiner(intel_dp)) {
> +		bigjoiner = true;
> +		max_dotclk *= 2;
> +	}
> +	if (target_clock > max_dotclk)
> +		return MODE_CLOCK_HIGH;
> +
>  	max_link_clock = intel_dp_max_link_rate(intel_dp);
>  	max_lanes = intel_dp_max_lane_count(intel_dp);
>  
> @@ -765,16 +806,23 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  							    max_link_clock,
>  							    max_lanes,
>  							    target_clock,
> -							    mode->hdisplay) >> 4;
> +							    mode->hdisplay,
> +							    bigjoiner) >> 4;
>  			dsc_slice_count =
>  				intel_dp_dsc_get_slice_count(intel_dp,
>  							     target_clock,
> -							     mode->hdisplay);
> +							     mode->hdisplay,
> +							     bigjoiner);
>  		}
> +
> +		dsc = dsc_max_output_bpp && dsc_slice_count;
>  	}
>  
> -	if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
> -	    target_clock > max_dotclk)
> +	/* big joiner configuration needs DSC */
> +	if (bigjoiner && !dsc)
> +		return MODE_CLOCK_HIGH;
> +
> +	if (mode_rate > max_rate && !dsc)
>  		return MODE_CLOCK_HIGH;
>  
>  	status = intel_dp_mode_valid_downstream(intel_connector,
> @@ -782,7 +830,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  	if (status != MODE_OK)
>  		return status;
>  
> -	return intel_mode_valid_max_plane_size(dev_priv, mode);
> +	return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
>  }
>  
>  u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
> @@ -2351,11 +2399,13 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  						    pipe_config->port_clock,
>  						    pipe_config->lane_count,
>  						    adjusted_mode->crtc_clock,
> -						    adjusted_mode->crtc_hdisplay);
> +						    adjusted_mode->crtc_hdisplay,
> +						    false);
>  		dsc_dp_slice_count =
>  			intel_dp_dsc_get_slice_count(intel_dp,
>  						     adjusted_mode->crtc_clock,
> -						     adjusted_mode->crtc_hdisplay);
> +						     adjusted_mode->crtc_hdisplay,
> +						     false);
>  		if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
>  			drm_dbg_kms(&dev_priv->drm,
>  				    "Compressed BPP/Slice Count not supported\n");
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 3f862b4fd34f..b871a09b6901 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -106,6 +106,7 @@ bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
>  bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
>  int intel_dp_link_required(int pixel_clock, int bpp);
>  int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
> +bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp);
>  bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
>  			    const struct drm_connector_state *conn_state);
>  void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index c8fcec4d0788..0c8684634fca 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -714,7 +714,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
>  		return 0;
>  	}
>  
> -	*status = intel_mode_valid_max_plane_size(dev_priv, mode);
> +	*status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
> index afa4e6817e8c..f453ceb8d149 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsi.c
> @@ -75,7 +75,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
>  			return MODE_CLOCK_HIGH;
>  	}
>  
> -	return intel_mode_valid_max_plane_size(dev_priv, mode);
> +	return intel_mode_valid_max_plane_size(dev_priv, mode, false);
>  }
>  
>  struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index f90838bc74fb..82674a8853c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2274,7 +2274,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
>  	if (status != MODE_OK)
>  		return status;
>  
> -	return intel_mode_valid_max_plane_size(dev_priv, mode);
> +	return intel_mode_valid_max_plane_size(dev_priv, mode, false);
>  }
>  
>  bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
> -- 
> 2.19.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
                   ` (4 preceding siblings ...)
  2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 6/6] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3 Manasi Navare
@ 2020-11-02 21:38 ` Patchwork
  2020-11-02 22:04 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
                   ` (9 subsequent siblings)
  15 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2020-11-02 21:38 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes
URL   : https://patchwork.freedesktop.org/series/83373/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b5a70599ee92 drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes
20fab9de7fd5 drm/i915: Move encoder->get_config to a new function
10c3667c3de6 drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
-:168: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#168: FILE: drivers/gpu/drm/i915/display/intel_display.c:13473:
+	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;

total: 0 errors, 0 warnings, 1 checks, 388 lines checked
792fb4cd8a71 drm/i915: Pass intel_atomic_state instead of drm_atomic_state
6c99d8e81e66 drm/i915/dp: Prep for bigjoiner atomic check
48259413d98d drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
                   ` (5 preceding siblings ...)
  2020-11-02 21:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Patchwork
@ 2020-11-02 22:04 ` Patchwork
  2020-11-02 23:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev2) Patchwork
                   ` (8 subsequent siblings)
  15 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2020-11-02 22:04 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 9920 bytes --]

== Series Details ==

Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes
URL   : https://patchwork.freedesktop.org/series/83373/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9247 -> Patchwork_18830
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18830 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18830, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18830:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-hsw-4770:        [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-hsw-4770/igt@kms_force_connector_basic@force-load-detect.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-hsw-4770/igt@kms_force_connector_basic@force-load-detect.html
    - fi-elk-e7500:       [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-elk-e7500/igt@kms_force_connector_basic@force-load-detect.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-elk-e7500/igt@kms_force_connector_basic@force-load-detect.html
    - fi-ivb-3770:        [PASS][5] -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-ivb-3770/igt@kms_force_connector_basic@force-load-detect.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-ivb-3770/igt@kms_force_connector_basic@force-load-detect.html
    - fi-byt-j1900:       [PASS][7] -> [FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-byt-j1900/igt@kms_force_connector_basic@force-load-detect.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-byt-j1900/igt@kms_force_connector_basic@force-load-detect.html
    - fi-blb-e6850:       [PASS][9] -> [INCOMPLETE][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-blb-e6850/igt@kms_force_connector_basic@force-load-detect.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-blb-e6850/igt@kms_force_connector_basic@force-load-detect.html
    - fi-ilk-650:         [PASS][11] -> [FAIL][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-ilk-650/igt@kms_force_connector_basic@force-load-detect.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-ilk-650/igt@kms_force_connector_basic@force-load-detect.html
    - fi-snb-2520m:       [PASS][13] -> [FAIL][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-snb-2520m/igt@kms_force_connector_basic@force-load-detect.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-snb-2520m/igt@kms_force_connector_basic@force-load-detect.html
    - fi-bwr-2160:        [PASS][15] -> [INCOMPLETE][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-bwr-2160/igt@kms_force_connector_basic@force-load-detect.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-bwr-2160/igt@kms_force_connector_basic@force-load-detect.html
    - fi-snb-2600:        [PASS][17] -> [FAIL][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-snb-2600/igt@kms_force_connector_basic@force-load-detect.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-snb-2600/igt@kms_force_connector_basic@force-load-detect.html

  * igt@runner@aborted:
    - fi-pnv-d510:        NOTRUN -> [FAIL][19]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-pnv-d510/igt@runner@aborted.html
    - fi-gdg-551:         NOTRUN -> [FAIL][20]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-gdg-551/igt@runner@aborted.html
    - fi-bwr-2160:        NOTRUN -> [FAIL][21]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-bwr-2160/igt@runner@aborted.html
    - fi-blb-e6850:       NOTRUN -> [FAIL][22]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-blb-e6850/igt@runner@aborted.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9247 and Patchwork_18830:

### New CI tests (1) ###

  * boot:
    - Statuses : 38 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18830 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload:
    - fi-icl-y:           [PASS][23] -> [DMESG-WARN][24] ([i915#1982])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-icl-y/igt@i915_module_load@reload.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-icl-y/igt@i915_module_load@reload.html

  * igt@i915_pm_rpm@module-reload:
    - fi-byt-j1900:       [PASS][25] -> [DMESG-WARN][26] ([i915#1982])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-icl-u2:          [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) +3 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-pnv-d510:        [PASS][29] -> [INCOMPLETE][30] ([i915#299])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-pnv-d510/igt@kms_force_connector_basic@force-load-detect.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-pnv-d510/igt@kms_force_connector_basic@force-load-detect.html
    - fi-gdg-551:         [PASS][31] -> [INCOMPLETE][32] ([i915#172])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-gdg-551/igt@kms_force_connector_basic@force-load-detect.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-gdg-551/igt@kms_force_connector_basic@force-load-detect.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - fi-apl-guc:         [DMESG-WARN][33] ([i915#1635] / [i915#1982]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-apl-guc/igt@i915_module_load@reload.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-apl-guc/igt@i915_module_load@reload.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-bsw-n3050:       [DMESG-WARN][35] ([i915#1982]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_selftest@live@gt_heartbeat:
    - {fi-tgl-dsi}:       [DMESG-FAIL][37] ([i915#2601]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_timelines:
    - fi-apl-guc:         [INCOMPLETE][39] ([i915#1635]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
    - fi-icl-u2:          [DMESG-WARN][41] ([i915#1982]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#172]: https://gitlab.freedesktop.org/drm/intel/issues/172
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601
  [i915#299]: https://gitlab.freedesktop.org/drm/intel/issues/299


Participating hosts (43 -> 38)
------------------------------

  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-kbl-7500u fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9247 -> Patchwork_18830

  CI-20190529: 20190529
  CI_DRM_9247: 009a99e9be393d32ed57bcac34d6b1fb37c28cdf @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5830: 12d370cb57e0cfcb781c87ad9e15e68b17a1f41f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18830: 48259413d98d37ad6fde949d14cfecbcf4510779 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

48259413d98d drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
6c99d8e81e66 drm/i915/dp: Prep for bigjoiner atomic check
792fb4cd8a71 drm/i915: Pass intel_atomic_state instead of drm_atomic_state
10c3667c3de6 drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
20fab9de7fd5 drm/i915: Move encoder->get_config to a new function
b5a70599ee92 drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18830/index.html

[-- Attachment #1.2: Type: text/html, Size: 11479 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev2)
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
                   ` (6 preceding siblings ...)
  2020-11-02 22:04 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-11-02 23:31 ` Patchwork
  2020-11-02 23:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
                   ` (7 subsequent siblings)
  15 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2020-11-02 23:31 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev2)
URL   : https://patchwork.freedesktop.org/series/83373/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
22e7ae4c328f drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes
7574de418b4b drm/i915: Move encoder->get_config to a new function
05d48230c4df drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
-:172: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#172: FILE: drivers/gpu/drm/i915/display/intel_display.c:13475:
+	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;

total: 0 errors, 0 warnings, 1 checks, 392 lines checked
3276c12fcaa1 drm/i915: Pass intel_atomic_state instead of drm_atomic_state
b376f9937d43 drm/i915/dp: Prep for bigjoiner atomic check
823f9a5b774b drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev2)
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
                   ` (7 preceding siblings ...)
  2020-11-02 23:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev2) Patchwork
@ 2020-11-02 23:56 ` Patchwork
  2020-11-03  7:25 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
                   ` (6 subsequent siblings)
  15 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2020-11-02 23:56 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 5543 bytes --]

== Series Details ==

Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev2)
URL   : https://patchwork.freedesktop.org/series/83373/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9247 -> Patchwork_18833
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/index.html

New tests
---------

  New tests have been introduced between CI_DRM_9247 and Patchwork_18833:

### New CI tests (1) ###

  * boot:
    - Statuses : 39 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18833 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload:
    - fi-icl-y:           [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-icl-y/igt@i915_module_load@reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/fi-icl-y/igt@i915_module_load@reload.html

  * igt@i915_pm_rpm@module-reload:
    - fi-byt-j1900:       [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-cml-u2:          [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-bsw-n3050:       [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-bsw-kefka:       [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_selftest@live@gt_heartbeat:
    - {fi-tgl-dsi}:       [DMESG-FAIL][11] ([i915#2601]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_timelines:
    - fi-apl-guc:         [INCOMPLETE][13] ([i915#1635]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - {fi-kbl-7560u}:     [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  
#### Warnings ####

  * igt@amdgpu/amd_prime@i915-to-amd:
    - fi-gdg-551:         [INCOMPLETE][17] ([i915#172]) -> [SKIP][18] ([fdo#109271])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-gdg-551/igt@amdgpu/amd_prime@i915-to-amd.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/fi-gdg-551/igt@amdgpu/amd_prime@i915-to-amd.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#172]: https://gitlab.freedesktop.org/drm/intel/issues/172
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601


Participating hosts (43 -> 39)
------------------------------

  Missing    (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u 


Build changes
-------------

  * Linux: CI_DRM_9247 -> Patchwork_18833

  CI-20190529: 20190529
  CI_DRM_9247: 009a99e9be393d32ed57bcac34d6b1fb37c28cdf @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5830: 12d370cb57e0cfcb781c87ad9e15e68b17a1f41f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18833: 823f9a5b774b441e66cc7b05170ed1fcd2390d17 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

823f9a5b774b drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
b376f9937d43 drm/i915/dp: Prep for bigjoiner atomic check
3276c12fcaa1 drm/i915: Pass intel_atomic_state instead of drm_atomic_state
05d48230c4df drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
7574de418b4b drm/i915: Move encoder->get_config to a new function
22e7ae4c328f drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/index.html

[-- Attachment #1.2: Type: text/html, Size: 6765 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev2)
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
                   ` (8 preceding siblings ...)
  2020-11-02 23:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-11-03  7:25 ` Patchwork
  2020-11-03 16:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev3) Patchwork
                   ` (5 subsequent siblings)
  15 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2020-11-03  7:25 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 18373 bytes --]

== Series Details ==

Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev2)
URL   : https://patchwork.freedesktop.org/series/83373/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9247_full -> Patchwork_18833_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18833_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18833_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18833_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-glk:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-glk2/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-glk5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9247_full and Patchwork_18833_full:

### New CI tests (1) ###

  * boot:
    - Statuses : 175 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18833_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_workarounds@suspend-resume:
    - shard-skl:          [PASS][3] -> [INCOMPLETE][4] ([i915#198])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl10/igt@gem_workarounds@suspend-resume.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl9/igt@gem_workarounds@suspend-resume.html

  * igt@i915_suspend@forcewake:
    - shard-kbl:          [PASS][5] -> [DMESG-WARN][6] ([i915#180])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-kbl6/igt@i915_suspend@forcewake.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-kbl2/igt@i915_suspend@forcewake.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
    - shard-kbl:          [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-kbl4/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-kbl6/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html

  * igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen:
    - shard-skl:          [PASS][9] -> [FAIL][10] ([i915#54]) +2 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html

  * igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge:
    - shard-glk:          [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-glk4/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-glk4/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html

  * igt@kms_flip@absolute-wf_vblank-interruptible@a-dp1:
    - shard-apl:          [PASS][13] -> [DMESG-WARN][14] ([i915#1635] / [i915#1982]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-apl3/igt@kms_flip@absolute-wf_vblank-interruptible@a-dp1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-apl3/igt@kms_flip@absolute-wf_vblank-interruptible@a-dp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([i915#79])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([i915#2122]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a1:
    - shard-glk:          [PASS][19] -> [FAIL][20] ([i915#2122])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-glk2/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a1.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-glk5/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
    - shard-tglb:         [PASS][21] -> [DMESG-WARN][22] ([i915#1982])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html

  * igt@kms_hdr@bpc-switch:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([i915#1188])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl7/igt@kms_hdr@bpc-switch.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl2/igt@kms_hdr@bpc-switch.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109441]) +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@perf@blocking:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([i915#1542])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl2/igt@perf@blocking.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl7/igt@perf@blocking.html

  * igt@perf@invalid-oa-exponent:
    - shard-skl:          [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +8 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl2/igt@perf@invalid-oa-exponent.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl7/igt@perf@invalid-oa-exponent.html

  * igt@sysfs_heartbeat_interval@mixed@vecs0:
    - shard-skl:          [PASS][31] -> [FAIL][32] ([i915#1731])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl2/igt@sysfs_heartbeat_interval@mixed@vecs0.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl8/igt@sysfs_heartbeat_interval@mixed@vecs0.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - shard-skl:          [DMESG-WARN][33] ([i915#1982]) -> [PASS][34] +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl10/igt@core_hotunplug@unbind-rebind.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl1/igt@core_hotunplug@unbind-rebind.html

  * igt@gem_exec_schedule@deep@vecs0:
    - shard-skl:          [INCOMPLETE][35] -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl3/igt@gem_exec_schedule@deep@vecs0.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl3/igt@gem_exec_schedule@deep@vecs0.html

  * igt@gem_pipe_control_store_loop@fresh-buffer:
    - shard-tglb:         [INCOMPLETE][37] -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-tglb1/igt@gem_pipe_control_store_loop@fresh-buffer.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-tglb5/igt@gem_pipe_control_store_loop@fresh-buffer.html

  * {igt@kms_async_flips@test-time-stamp}:
    - shard-apl:          [DMESG-WARN][39] ([i915#1635] / [i915#1982]) -> [PASS][40] +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-apl4/igt@kms_async_flips@test-time-stamp.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-apl1/igt@kms_async_flips@test-time-stamp.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
    - shard-skl:          [FAIL][41] ([i915#54]) -> [PASS][42] +3 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [FAIL][43] ([i915#2346]) -> [PASS][44] +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][45] ([i915#2122]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-glk9/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-glk2/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@dpms-vs-vblank-race@b-dp1:
    - shard-kbl:          [INCOMPLETE][47] -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-kbl6/igt@kms_flip@dpms-vs-vblank-race@b-dp1.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-kbl2/igt@kms_flip@dpms-vs-vblank-race@b-dp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-skl:          [FAIL][49] ([i915#79]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip_tiling@flip-x-tiled:
    - shard-kbl:          [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-kbl4/igt@kms_flip_tiling@flip-x-tiled.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-kbl6/igt@kms_flip_tiling@flip-x-tiled.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
    - shard-iclb:         [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-iclb3/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-iclb5/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
    - shard-tglb:         [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-tglb2/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-tglb7/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-c:
    - shard-skl:          [FAIL][57] -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl2/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-c.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl7/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-c.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-iclb:         [INCOMPLETE][59] ([i915#1185] / [i915#250]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-iclb4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][61] ([fdo#108145] / [i915#265]) -> [PASS][62] +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [SKIP][63] ([fdo#109441]) -> [PASS][64] +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_sequence@queue-idle:
    - shard-skl:          [FAIL][65] ([i915#2441]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl3/igt@kms_sequence@queue-idle.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl3/igt@kms_sequence@queue-idle.html

  * igt@sysfs_heartbeat_interval@mixed@bcs0:
    - shard-skl:          [FAIL][67] ([i915#1731]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl2/igt@sysfs_heartbeat_interval@mixed@bcs0.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-skl8/igt@sysfs_heartbeat_interval@mixed@bcs0.html

  
#### Warnings ####

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - shard-snb:          [FAIL][69] -> [INCOMPLETE][70] ([i915#82])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-snb7/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-snb7/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][71] ([i915#658]) -> [SKIP][72] ([i915#588])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
    - shard-tglb:         [DMESG-WARN][73] ([i915#2411]) -> [INCOMPLETE][74] ([i915#1436] / [i915#456])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-tglb7/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-tglb1/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html

  * igt@runner@aborted:
    - shard-tglb:         ([FAIL][75], [FAIL][76]) ([i915#2439]) -> ([FAIL][77], [FAIL][78]) ([i915#2248] / [i915#2439])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-tglb1/igt@runner@aborted.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-tglb2/igt@runner@aborted.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-tglb1/igt@runner@aborted.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/shard-tglb8/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2248]: https://gitlab.freedesktop.org/drm/intel/issues/2248
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#2441]: https://gitlab.freedesktop.org/drm/intel/issues/2441
  [i915#250]: https://gitlab.freedesktop.org/drm/intel/issues/250
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9247 -> Patchwork_18833

  CI-20190529: 20190529
  CI_DRM_9247: 009a99e9be393d32ed57bcac34d6b1fb37c28cdf @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5830: 12d370cb57e0cfcb781c87ad9e15e68b17a1f41f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18833: 823f9a5b774b441e66cc7b05170ed1fcd2390d17 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18833/index.html

[-- Attachment #1.2: Type: text/html, Size: 21041 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev3)
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
                   ` (9 preceding siblings ...)
  2020-11-03  7:25 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-11-03 16:34 ` Patchwork
  2020-11-03 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
                   ` (4 subsequent siblings)
  15 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2020-11-03 16:34 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev3)
URL   : https://patchwork.freedesktop.org/series/83373/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
ef45baae1b4d drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes
54c92c312833 drm/i915: Move encoder->get_config to a new function
fa9cc802e92e drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
-:172: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#172: FILE: drivers/gpu/drm/i915/display/intel_display.c:13475:
+	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;

total: 0 errors, 0 warnings, 1 checks, 392 lines checked
bd6d793e3861 drm/i915: Pass intel_atomic_state instead of drm_atomic_state
7004b13da2f6 drm/i915/dp: Prep for bigjoiner atomic check
d4ce6b762592 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
-:191: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line
#191: FILE: drivers/gpu/drm/i915/display/intel_dp.c:774:
+	if ((target_clock > max_dotclk || mode->hdisplay > 5120)
+	    && intel_dp_can_bigjoiner(intel_dp)) {

total: 0 errors, 0 warnings, 1 checks, 211 lines checked


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev3)
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
                   ` (10 preceding siblings ...)
  2020-11-03 16:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev3) Patchwork
@ 2020-11-03 16:53 ` Patchwork
  2020-11-03 22:52 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
                   ` (3 subsequent siblings)
  15 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2020-11-03 16:53 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 3990 bytes --]

== Series Details ==

Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev3)
URL   : https://patchwork.freedesktop.org/series/83373/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9255 -> Patchwork_18843
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/index.html

New tests
---------

  New tests have been introduced between CI_DRM_9255 and Patchwork_18843:

### New CI tests (1) ###

  * boot:
    - Statuses : 38 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18843 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload:
    - fi-tgl-u2:          [PASS][1] -> [DMESG-WARN][2] ([i915#1982] / [k.org#205379])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-tgl-u2/igt@i915_module_load@reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/fi-tgl-u2/igt@i915_module_load@reload.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-bsw-kefka:       [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - fi-icl-y:           [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-icl-y/igt@i915_module_load@reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/fi-icl-y/igt@i915_module_load@reload.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-byt-j1900:       [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
    - fi-icl-u2:          [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html

  
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379


Participating hosts (42 -> 38)
------------------------------

  Missing    (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u 


Build changes
-------------

  * Linux: CI_DRM_9255 -> Patchwork_18843

  CI-20190529: 20190529
  CI_DRM_9255: 10bed1eeb88d1ebe8f7b00b57c37329068b06ca4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5830: 12d370cb57e0cfcb781c87ad9e15e68b17a1f41f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18843: d4ce6b762592e81747632f613162cff88a1bdf26 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

d4ce6b762592 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
7004b13da2f6 drm/i915/dp: Prep for bigjoiner atomic check
bd6d793e3861 drm/i915: Pass intel_atomic_state instead of drm_atomic_state
fa9cc802e92e drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
54c92c312833 drm/i915: Move encoder->get_config to a new function
ef45baae1b4d drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/index.html

[-- Attachment #1.2: Type: text/html, Size: 5040 bytes --]

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev3)
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
                   ` (11 preceding siblings ...)
  2020-11-03 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-11-03 22:52 ` Patchwork
  2020-11-12  0:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev4) Patchwork
                   ` (2 subsequent siblings)
  15 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2020-11-03 22:52 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 18014 bytes --]

== Series Details ==

Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev3)
URL   : https://patchwork.freedesktop.org/series/83373/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9255_full -> Patchwork_18843_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

New tests
---------

  New tests have been introduced between CI_DRM_9255_full and Patchwork_18843_full:

### New CI tests (1) ###

  * boot:
    - Statuses : 175 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18843_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_blits@basic:
    - shard-skl:          [PASS][1] -> [TIMEOUT][2] ([i915#2502])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl6/igt@gem_blits@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl3/igt@gem_blits@basic.html

  * igt@i915_pm_rpm@gem-mmap-type@uc:
    - shard-skl:          [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +5 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl4/igt@i915_pm_rpm@gem-mmap-type@uc.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl2/igt@i915_pm_rpm@gem-mmap-type@uc.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [PASS][5] -> [DMESG-WARN][6] ([i915#180])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding:
    - shard-skl:          [PASS][7] -> [FAIL][8] ([i915#54]) +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding.html

  * igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge:
    - shard-glk:          [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-glk6/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-glk7/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([i915#2346])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([i915#79])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a2:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#2122])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-glk5/igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a2.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-glk3/igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a2.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([i915#2122]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html

  * igt@kms_flip_tiling@flip-to-yf-tiled:
    - shard-kbl:          [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-kbl3/igt@kms_flip_tiling@flip-to-yf-tiled.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-kbl6/igt@kms_flip_tiling@flip-to-yf-tiled.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][21] -> [FAIL][22] ([i915#1188]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl3/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109441]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_vblank@pipe-d-accuracy-idle:
    - shard-tglb:         [PASS][27] -> [DMESG-WARN][28] ([i915#1982])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-tglb8/igt@kms_vblank@pipe-d-accuracy-idle.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-tglb7/igt@kms_vblank@pipe-d-accuracy-idle.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [PASS][29] -> [FAIL][30] ([i915#1542])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl4/igt@perf@polling-parameterized.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl6/igt@perf@polling-parameterized.html

  * igt@perf_pmu@module-unload:
    - shard-apl:          [PASS][31] -> [DMESG-WARN][32] ([i915#1635] / [i915#1982])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-apl1/igt@perf_pmu@module-unload.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-apl3/igt@perf_pmu@module-unload.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3:
    - shard-skl:          [INCOMPLETE][33] ([i915#198]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl2/igt@gem_exec_suspend@basic-s3.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl4/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_exec_whisper@basic-queues-all:
    - shard-glk:          [DMESG-WARN][35] ([i915#118] / [i915#95]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-glk8/igt@gem_exec_whisper@basic-queues-all.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-glk2/igt@gem_exec_whisper@basic-queues-all.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-iclb:         [DMESG-WARN][37] ([i915#1982]) -> [PASS][38] +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-iclb5/igt@i915_module_load@reload-with-fault-injection.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-iclb4/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_backlight@fade_with_suspend:
    - shard-skl:          [INCOMPLETE][39] -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl3/igt@i915_pm_backlight@fade_with_suspend.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl8/igt@i915_pm_backlight@fade_with_suspend.html

  * igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen:
    - shard-skl:          [FAIL][41] ([i915#54]) -> [PASS][42] +4 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html

  * igt@kms_cursor_edge_walk@pipe-c-256x256-top-edge:
    - shard-kbl:          [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-kbl7/igt@kms_cursor_edge_walk@pipe-c-256x256-top-edge.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-kbl1/igt@kms_cursor_edge_walk@pipe-c-256x256-top-edge.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-glk:          [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-glk8/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-glk2/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-skl:          [DMESG-WARN][47] ([i915#1982]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl8/igt@kms_fbcon_fbt@psr-suspend.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl2/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
    - shard-skl:          [FAIL][49] ([i915#2122]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render:
    - shard-kbl:          [INCOMPLETE][51] -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-c:
    - shard-skl:          [FAIL][53] -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl8/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-c.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl2/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][55] ([fdo#108145] / [i915#265]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_plane_cursor@pipe-a-overlay-size-64:
    - shard-apl:          [DMESG-WARN][57] ([i915#1635] / [i915#1982]) -> [PASS][58] +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-apl1/igt@kms_plane_cursor@pipe-a-overlay-size-64.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-apl3/igt@kms_plane_cursor@pipe-a-overlay-size-64.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [SKIP][59] ([fdo#109642] / [fdo#111068]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-iclb4/igt@kms_psr2_su@frontbuffer.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-iclb2/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [SKIP][61] ([fdo#109441]) -> [PASS][62] +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-iclb4/igt@kms_psr@psr2_cursor_plane_move.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@perf@polling-parameterized:
    - shard-iclb:         [FAIL][63] ([i915#1542]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-iclb3/igt@perf@polling-parameterized.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-iclb6/igt@perf@polling-parameterized.html

  * igt@sysfs_heartbeat_interval@mixed@vecs0:
    - shard-skl:          [FAIL][65] ([i915#1731]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl8/igt@sysfs_heartbeat_interval@mixed@vecs0.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl2/igt@sysfs_heartbeat_interval@mixed@vecs0.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
    - shard-tglb:         [DMESG-WARN][67] ([i915#2411]) -> [INCOMPLETE][68] ([i915#1436] / [i915#456])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-tglb8/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-tglb2/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html

  * igt@kms_flip_tiling@flip-x-tiled:
    - shard-skl:          [DMESG-WARN][69] ([i915#1982]) -> [DMESG-FAIL][70] ([fdo#108145] / [i915#1982])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl9/igt@kms_flip_tiling@flip-x-tiled.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl7/igt@kms_flip_tiling@flip-x-tiled.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-apl:          [FAIL][71] ([fdo#108145] / [i915#1635] / [i915#265]) -> [DMESG-FAIL][72] ([fdo#108145] / [i915#1635] / [i915#1982])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@runner@aborted:
    - shard-iclb:         [FAIL][73] ([i915#1814] / [i915#483]) -> [FAIL][74] ([i915#1814])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-iclb7/igt@runner@aborted.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-iclb4/igt@runner@aborted.html
    - shard-tglb:         [FAIL][75] ([i915#2439]) -> ([FAIL][76], [FAIL][77]) ([i915#2248] / [i915#2439])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-tglb6/igt@runner@aborted.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-tglb2/igt@runner@aborted.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-tglb8/igt@runner@aborted.html
    - shard-skl:          ([FAIL][78], [FAIL][79]) ([i915#1436] / [i915#2029] / [i915#2439]) -> [FAIL][80] ([i915#1436])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl8/igt@runner@aborted.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9255/shard-skl3/igt@runner@aborted.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/shard-skl2/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2248]: https://gitlab.freedesktop.org/drm/intel/issues/2248
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9255 -> Patchwork_18843

  CI-20190529: 20190529
  CI_DRM_9255: 10bed1eeb88d1ebe8f7b00b57c37329068b06ca4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5830: 12d370cb57e0cfcb781c87ad9e15e68b17a1f41f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18843: d4ce6b762592e81747632f613162cff88a1bdf26 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18843/index.html

[-- Attachment #1.2: Type: text/html, Size: 21577 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev4)
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
                   ` (12 preceding siblings ...)
  2020-11-03 22:52 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-11-12  0:32 ` Patchwork
  2020-11-12  1:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
  2020-11-12  4:09 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
  15 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2020-11-12  0:32 UTC (permalink / raw)
  To: Navare, Manasi; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev4)
URL   : https://patchwork.freedesktop.org/series/83373/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
56832962f07a drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes
5fae0b39d724 drm/i915: Move encoder->get_config to a new function
f7a41ea3fe88 drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
-:172: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#172: FILE: drivers/gpu/drm/i915/display/intel_display.c:13403:
+	crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;

total: 0 errors, 0 warnings, 1 checks, 392 lines checked
a7e4860f25c4 drm/i915: Pass intel_atomic_state instead of drm_atomic_state
201455d23ee8 drm/i915/dp: Prep for bigjoiner atomic check
8be57882b8f8 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
-:195: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line
#195: FILE: drivers/gpu/drm/i915/display/intel_dp.c:774:
+	if ((target_clock > max_dotclk || mode->hdisplay > 5120)
+	    && intel_dp_can_bigjoiner(intel_dp)) {

total: 0 errors, 0 warnings, 1 checks, 211 lines checked


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev4)
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
                   ` (13 preceding siblings ...)
  2020-11-12  0:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev4) Patchwork
@ 2020-11-12  1:02 ` Patchwork
  2020-11-12  4:09 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
  15 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2020-11-12  1:02 UTC (permalink / raw)
  To: Navare, Manasi; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 3790 bytes --]

== Series Details ==

Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev4)
URL   : https://patchwork.freedesktop.org/series/83373/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9312 -> Patchwork_18891
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/index.html

New tests
---------

  New tests have been introduced between CI_DRM_9312 and Patchwork_18891:

### New CI tests (1) ###

  * boot:
    - Statuses : 40 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18891 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-icl-u2:          [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_pm_rpm@module-reload:
    - fi-byt-j1900:       [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html

  
#### Possible fixes ####

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-byt-j1900:       [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - fi-icl-u2:          [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2417]: https://gitlab.freedesktop.org/drm/intel/issues/2417


Participating hosts (44 -> 40)
------------------------------

  Additional (1): fi-tgl-y 
  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-kbl-8809g fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9312 -> Patchwork_18891

  CI-20190529: 20190529
  CI_DRM_9312: 88b74d59a27aa168f7cd2dec199c33ee71fe8bb0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5847: 8cffaebec5228a5042cc6928ac582a0589e2de3e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18891: 8be57882b8f8fe53a333e8d9cf72d779096b0cd1 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

8be57882b8f8 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
201455d23ee8 drm/i915/dp: Prep for bigjoiner atomic check
a7e4860f25c4 drm/i915: Pass intel_atomic_state instead of drm_atomic_state
f7a41ea3fe88 drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
5fae0b39d724 drm/i915: Move encoder->get_config to a new function
56832962f07a drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/index.html

[-- Attachment #1.2: Type: text/html, Size: 4699 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev4)
  2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
                   ` (14 preceding siblings ...)
  2020-11-12  1:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-11-12  4:09 ` Patchwork
  2020-11-12  6:29   ` Navare, Manasi
  15 siblings, 1 reply; 32+ messages in thread
From: Patchwork @ 2020-11-12  4:09 UTC (permalink / raw)
  To: Manasi Navare; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 19297 bytes --]

== Series Details ==

Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev4)
URL   : https://patchwork.freedesktop.org/series/83373/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9312_full -> Patchwork_18891_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18891_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18891_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18891_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_create@create-clear:
    - shard-snb:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-snb2/igt@gem_create@create-clear.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - shard-iclb:         [PASS][2] -> [FAIL][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb2/igt@i915_pm_rpm@basic-pci-d3-state.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-iclb5/igt@i915_pm_rpm@basic-pci-d3-state.html

  
#### Warnings ####

  * igt@runner@aborted:
    - shard-hsw:          ([FAIL][4], [FAIL][5]) ([i915#1436] / [i915#2439] / [i915#483]) -> ([FAIL][6], [FAIL][7]) ([i915#1436] / [i915#2439])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw6/igt@runner@aborted.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw1/igt@runner@aborted.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-hsw8/igt@runner@aborted.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-hsw6/igt@runner@aborted.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9312_full and Patchwork_18891_full:

### New CI tests (1) ###

  * boot:
    - Statuses : 199 pass(s)
    - Exec time: [0.0] s

  


### New IGT tests (1) ###

  * igt@sysfs_defaults@readonly:
    - Statuses :
    - Exec time: [None] s

  

Known issues
------------

  Here are the changes found in Patchwork_18891_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_whisper@basic-forked:
    - shard-glk:          [PASS][8] -> [DMESG-WARN][9] ([i915#118] / [i915#95])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk8/igt@gem_exec_whisper@basic-forked.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-glk3/igt@gem_exec_whisper@basic-forked.html

  * igt@kms_big_fb@linear-32bpp-rotate-180:
    - shard-kbl:          [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +3 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-kbl4/igt@kms_big_fb@linear-32bpp-rotate-180.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-kbl3/igt@kms_big_fb@linear-32bpp-rotate-180.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
    - shard-skl:          [PASS][12] -> [FAIL][13] ([i915#54]) +2 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html

  * igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge:
    - shard-glk:          [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk7/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-glk7/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html

  * igt@kms_cursor_edge_walk@pipe-d-64x64-top-edge:
    - shard-tglb:         [PASS][16] -> [DMESG-WARN][17] ([i915#1982]) +2 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb3/igt@kms_cursor_edge_walk@pipe-d-64x64-top-edge.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-tglb1/igt@kms_cursor_edge_walk@pipe-d-64x64-top-edge.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [PASS][18] -> [FAIL][19] ([i915#2346])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@absolute-wf_vblank-interruptible@a-dp1:
    - shard-apl:          [PASS][20] -> [DMESG-WARN][21] ([i915#1635] / [i915#1982])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-apl4/igt@kms_flip@absolute-wf_vblank-interruptible@a-dp1.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-apl8/igt@kms_flip@absolute-wf_vblank-interruptible@a-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate@a-edp1:
    - shard-skl:          [PASS][22] -> [FAIL][23] ([i915#2122])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][24] -> [FAIL][25] ([i915#1188])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [PASS][26] -> [INCOMPLETE][27] ([i915#1635] / [i915#2377])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_lowres@pipe-a-tiling-yf:
    - shard-skl:          [PASS][28] -> [DMESG-WARN][29] ([i915#1982]) +8 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@kms_plane_lowres@pipe-a-tiling-yf.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl9/igt@kms_plane_lowres@pipe-a-tiling-yf.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [PASS][30] -> [SKIP][31] ([fdo#109441]) +1 similar issue
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-iclb3/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@perf@polling-parameterized:
    - shard-glk:          [PASS][32] -> [FAIL][33] ([i915#1542])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk5/igt@perf@polling-parameterized.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-glk1/igt@perf@polling-parameterized.html

  
#### Possible fixes ####

  * igt@gem_exec_create@basic:
    - shard-snb:          [FAIL][34] ([i915#1037]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-snb7/igt@gem_exec_create@basic.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-snb2/igt@gem_exec_create@basic.html

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [INCOMPLETE][36] ([i915#198]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@gem_softpin@noreloc-s3.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl7/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-hsw:          [FAIL][38] ([i915#1888]) -> [PASS][39] +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw8/igt@gem_userptr_blits@unsync-unmap-cycles.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-hsw6/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-skl:          [DMESG-WARN][40] ([i915#1436] / [i915#716]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@gen9_exec_parse@allowed-all.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl7/igt@gen9_exec_parse@allowed-all.html

  * {igt@kms_async_flips@alternate-sync-async-flip}:
    - shard-tglb:         [FAIL][42] ([i915#2521]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb1/igt@kms_async_flips@alternate-sync-async-flip.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-tglb5/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-random:
    - shard-skl:          [FAIL][44] ([i915#54]) -> [PASS][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html

  * igt@kms_cursor_legacy@short-flip-before-cursor-toggle:
    - shard-apl:          [DMESG-WARN][46] ([i915#1635] / [i915#1982]) -> [PASS][47] +2 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-apl7/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-apl7/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled:
    - shard-skl:          [DMESG-WARN][48] ([i915#1982]) -> [PASS][49] +4 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl7/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
    - shard-skl:          [FAIL][50] ([i915#2122]) -> [PASS][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html

  * igt@kms_frontbuffer_tracking@basic:
    - shard-glk:          [DMESG-WARN][52] ([i915#1982]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk1/igt@kms_frontbuffer_tracking@basic.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-glk5/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite:
    - shard-kbl:          [DMESG-WARN][54] ([i915#1982]) -> [PASS][55]
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu:
    - shard-tglb:         [DMESG-WARN][56] ([i915#1982]) -> [PASS][57]
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html

  * igt@kms_psr@psr2_dpms:
    - shard-iclb:         [SKIP][58] ([fdo#109441]) -> [PASS][59] +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb6/igt@kms_psr@psr2_dpms.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-iclb2/igt@kms_psr@psr2_dpms.html

  * igt@kms_vblank@pipe-c-query-forked-busy:
    - shard-hsw:          [DMESG-WARN][60] ([i915#1982]) -> [PASS][61] +1 similar issue
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw6/igt@kms_vblank@pipe-c-query-forked-busy.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-hsw4/igt@kms_vblank@pipe-c-query-forked-busy.html
    - shard-iclb:         [DMESG-WARN][62] ([i915#1982]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb7/igt@kms_vblank@pipe-c-query-forked-busy.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-iclb6/igt@kms_vblank@pipe-c-query-forked-busy.html

  * igt@perf@short-reads:
    - shard-skl:          [FAIL][64] ([i915#51]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl4/igt@perf@short-reads.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl1/igt@perf@short-reads.html

  
#### Warnings ####

  * igt@gem_eio@in-flight-suspend:
    - shard-tglb:         [INCOMPLETE][66] ([i915#1436] / [i915#456]) -> [DMESG-WARN][67] ([i915#1436])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb7/igt@gem_eio@in-flight-suspend.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-tglb2/igt@gem_eio@in-flight-suspend.html
    - shard-glk:          [DMESG-WARN][68] ([i915#2635]) -> [INCOMPLETE][69] ([i915#2635])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk4/igt@gem_eio@in-flight-suspend.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-glk6/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_create@forked:
    - shard-glk:          [FAIL][70] -> [FAIL][71] ([i915#1888])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk8/igt@gem_exec_create@forked.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-glk2/igt@gem_exec_create@forked.html
    - shard-hsw:          [FAIL][72] -> [FAIL][73] ([i915#1888])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw8/igt@gem_exec_create@forked.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-hsw6/igt@gem_exec_create@forked.html

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-skl:          [SKIP][74] ([fdo#109271] / [i915#658]) -> [INCOMPLETE][75] ([i915#198])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl9/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl9/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [SKIP][76] ([fdo#109349]) -> [DMESG-WARN][77] ([i915#1226])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-tglb:         [DMESG-WARN][78] ([i915#2411]) -> [DMESG-WARN][79] ([i915#1982] / [i915#2411])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-tglb2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-tglb:         [INCOMPLETE][80] ([i915#1436] / [i915#456]) -> [INCOMPLETE][81] ([i915#1436])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb1/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-tglb5/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html

  * igt@runner@aborted:
    - shard-skl:          ([FAIL][82], [FAIL][83]) ([i915#1436] / [i915#1611] / [i915#2439] / [i915#483]) -> [FAIL][84] ([i915#1611] / [i915#2439])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@runner@aborted.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl6/igt@runner@aborted.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl10/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2377]: https://gitlab.freedesktop.org/drm/intel/issues/2377
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2635]: https://gitlab.freedesktop.org/drm/intel/issues/2635
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
  [i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9312 -> Patchwork_18891

  CI-20190529: 20190529
  CI_DRM_9312: 88b74d59a27aa168f7cd2dec199c33ee71fe8bb0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5847: 8cffaebec5228a5042cc6928ac582a0589e2de3e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18891: 8be57882b8f8fe53a333e8d9cf72d779096b0cd1 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/index.html

[-- Attachment #1.2: Type: text/html, Size: 23290 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

* Re: [Intel-gfx]  ✗ Fi.CI.IGT: failure for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev4)
  2020-11-12  4:09 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-11-12  6:29   ` Navare, Manasi
  0 siblings, 0 replies; 32+ messages in thread
From: Navare, Manasi @ 2020-11-12  6:29 UTC (permalink / raw)
  To: intel-gfx

On Thu, Nov 12, 2020 at 04:09:14AM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev4)
> URL   : https://patchwork.freedesktop.org/series/83373/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_9312_full -> Patchwork_18891_full
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_18891_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_18891_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in Patchwork_18891_full:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@gem_create@create-clear:
>     - shard-snb:          NOTRUN -> [INCOMPLETE][1]
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-snb2/igt@gem_create@create-clear.html

This gem_create fail looks unrelated 

> 
>   * igt@i915_pm_rpm@basic-pci-d3-state:
>     - shard-iclb:         [PASS][2] -> [FAIL][3]
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb2/igt@i915_pm_rpm@basic-pci-d3-state.html
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-iclb5/igt@i915_pm_rpm@basic-pci-d3-state.html

This looks unrelated
Can this be marked as unrelated/ false errors so we can go ahead with upstreaming?

Manasi

> 
>   
> #### Warnings ####
> 
>   * igt@runner@aborted:
>     - shard-hsw:          ([FAIL][4], [FAIL][5]) ([i915#1436] / [i915#2439] / [i915#483]) -> ([FAIL][6], [FAIL][7]) ([i915#1436] / [i915#2439])
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw6/igt@runner@aborted.html
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw1/igt@runner@aborted.html
>    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-hsw8/igt@runner@aborted.html
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-hsw6/igt@runner@aborted.html
> 
>   
> New tests
> ---------
> 
>   New tests have been introduced between CI_DRM_9312_full and Patchwork_18891_full:
> 
> ### New CI tests (1) ###
> 
>   * boot:
>     - Statuses : 199 pass(s)
>     - Exec time: [0.0] s
> 
>   
> 
> 
> ### New IGT tests (1) ###
> 
>   * igt@sysfs_defaults@readonly:
>     - Statuses :
>     - Exec time: [None] s
> 
>   
> 
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_18891_full that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_exec_whisper@basic-forked:
>     - shard-glk:          [PASS][8] -> [DMESG-WARN][9] ([i915#118] / [i915#95])
>    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk8/igt@gem_exec_whisper@basic-forked.html
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-glk3/igt@gem_exec_whisper@basic-forked.html
> 
>   * igt@kms_big_fb@linear-32bpp-rotate-180:
>     - shard-kbl:          [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +3 similar issues
>    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-kbl4/igt@kms_big_fb@linear-32bpp-rotate-180.html
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-kbl3/igt@kms_big_fb@linear-32bpp-rotate-180.html
> 
>   * igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
>     - shard-skl:          [PASS][12] -> [FAIL][13] ([i915#54]) +2 similar issues
>    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
>    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
> 
>   * igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge:
>     - shard-glk:          [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) +1 similar issue
>    [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk7/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html
>    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-glk7/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html
> 
>   * igt@kms_cursor_edge_walk@pipe-d-64x64-top-edge:
>     - shard-tglb:         [PASS][16] -> [DMESG-WARN][17] ([i915#1982]) +2 similar issues
>    [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb3/igt@kms_cursor_edge_walk@pipe-d-64x64-top-edge.html
>    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-tglb1/igt@kms_cursor_edge_walk@pipe-d-64x64-top-edge.html
> 
>   * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
>     - shard-skl:          [PASS][18] -> [FAIL][19] ([i915#2346])
>    [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
>    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
> 
>   * igt@kms_flip@absolute-wf_vblank-interruptible@a-dp1:
>     - shard-apl:          [PASS][20] -> [DMESG-WARN][21] ([i915#1635] / [i915#1982])
>    [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-apl4/igt@kms_flip@absolute-wf_vblank-interruptible@a-dp1.html
>    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-apl8/igt@kms_flip@absolute-wf_vblank-interruptible@a-dp1.html
> 
>   * igt@kms_flip@plain-flip-fb-recreate@a-edp1:
>     - shard-skl:          [PASS][22] -> [FAIL][23] ([i915#2122])
>    [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
>    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
> 
>   * igt@kms_hdr@bpc-switch-dpms:
>     - shard-skl:          [PASS][24] -> [FAIL][25] ([i915#1188])
>    [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
>    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
> 
>   * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
>     - shard-apl:          [PASS][26] -> [INCOMPLETE][27] ([i915#1635] / [i915#2377])
>    [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
>    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> 
>   * igt@kms_plane_lowres@pipe-a-tiling-yf:
>     - shard-skl:          [PASS][28] -> [DMESG-WARN][29] ([i915#1982]) +8 similar issues
>    [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@kms_plane_lowres@pipe-a-tiling-yf.html
>    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl9/igt@kms_plane_lowres@pipe-a-tiling-yf.html
> 
>   * igt@kms_psr@psr2_cursor_plane_move:
>     - shard-iclb:         [PASS][30] -> [SKIP][31] ([fdo#109441]) +1 similar issue
>    [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
>    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-iclb3/igt@kms_psr@psr2_cursor_plane_move.html
> 
>   * igt@perf@polling-parameterized:
>     - shard-glk:          [PASS][32] -> [FAIL][33] ([i915#1542])
>    [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk5/igt@perf@polling-parameterized.html
>    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-glk1/igt@perf@polling-parameterized.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_exec_create@basic:
>     - shard-snb:          [FAIL][34] ([i915#1037]) -> [PASS][35]
>    [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-snb7/igt@gem_exec_create@basic.html
>    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-snb2/igt@gem_exec_create@basic.html
> 
>   * igt@gem_softpin@noreloc-s3:
>     - shard-skl:          [INCOMPLETE][36] ([i915#198]) -> [PASS][37]
>    [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@gem_softpin@noreloc-s3.html
>    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl7/igt@gem_softpin@noreloc-s3.html
> 
>   * igt@gem_userptr_blits@unsync-unmap-cycles:
>     - shard-hsw:          [FAIL][38] ([i915#1888]) -> [PASS][39] +1 similar issue
>    [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw8/igt@gem_userptr_blits@unsync-unmap-cycles.html
>    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-hsw6/igt@gem_userptr_blits@unsync-unmap-cycles.html
> 
>   * igt@gen9_exec_parse@allowed-all:
>     - shard-skl:          [DMESG-WARN][40] ([i915#1436] / [i915#716]) -> [PASS][41]
>    [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@gen9_exec_parse@allowed-all.html
>    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl7/igt@gen9_exec_parse@allowed-all.html
> 
>   * {igt@kms_async_flips@alternate-sync-async-flip}:
>     - shard-tglb:         [FAIL][42] ([i915#2521]) -> [PASS][43]
>    [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb1/igt@kms_async_flips@alternate-sync-async-flip.html
>    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-tglb5/igt@kms_async_flips@alternate-sync-async-flip.html
> 
>   * igt@kms_cursor_crc@pipe-c-cursor-64x21-random:
>     - shard-skl:          [FAIL][44] ([i915#54]) -> [PASS][45]
>    [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html
>    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html
> 
>   * igt@kms_cursor_legacy@short-flip-before-cursor-toggle:
>     - shard-apl:          [DMESG-WARN][46] ([i915#1635] / [i915#1982]) -> [PASS][47] +2 similar issues
>    [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-apl7/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html
>    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-apl7/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html
> 
>   * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled:
>     - shard-skl:          [DMESG-WARN][48] ([i915#1982]) -> [PASS][49] +4 similar issues
>    [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html
>    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl7/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html
> 
>   * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
>     - shard-skl:          [FAIL][50] ([i915#2122]) -> [PASS][51]
>    [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
>    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
> 
>   * igt@kms_frontbuffer_tracking@basic:
>     - shard-glk:          [DMESG-WARN][52] ([i915#1982]) -> [PASS][53]
>    [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk1/igt@kms_frontbuffer_tracking@basic.html
>    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-glk5/igt@kms_frontbuffer_tracking@basic.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite:
>     - shard-kbl:          [DMESG-WARN][54] ([i915#1982]) -> [PASS][55]
>    [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html
>    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu:
>     - shard-tglb:         [DMESG-WARN][56] ([i915#1982]) -> [PASS][57]
>    [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html
>    [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html
> 
>   * igt@kms_psr@psr2_dpms:
>     - shard-iclb:         [SKIP][58] ([fdo#109441]) -> [PASS][59] +1 similar issue
>    [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb6/igt@kms_psr@psr2_dpms.html
>    [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-iclb2/igt@kms_psr@psr2_dpms.html
> 
>   * igt@kms_vblank@pipe-c-query-forked-busy:
>     - shard-hsw:          [DMESG-WARN][60] ([i915#1982]) -> [PASS][61] +1 similar issue
>    [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw6/igt@kms_vblank@pipe-c-query-forked-busy.html
>    [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-hsw4/igt@kms_vblank@pipe-c-query-forked-busy.html
>     - shard-iclb:         [DMESG-WARN][62] ([i915#1982]) -> [PASS][63]
>    [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb7/igt@kms_vblank@pipe-c-query-forked-busy.html
>    [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-iclb6/igt@kms_vblank@pipe-c-query-forked-busy.html
> 
>   * igt@perf@short-reads:
>     - shard-skl:          [FAIL][64] ([i915#51]) -> [PASS][65]
>    [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl4/igt@perf@short-reads.html
>    [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl1/igt@perf@short-reads.html
> 
>   
> #### Warnings ####
> 
>   * igt@gem_eio@in-flight-suspend:
>     - shard-tglb:         [INCOMPLETE][66] ([i915#1436] / [i915#456]) -> [DMESG-WARN][67] ([i915#1436])
>    [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb7/igt@gem_eio@in-flight-suspend.html
>    [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-tglb2/igt@gem_eio@in-flight-suspend.html
>     - shard-glk:          [DMESG-WARN][68] ([i915#2635]) -> [INCOMPLETE][69] ([i915#2635])
>    [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk4/igt@gem_eio@in-flight-suspend.html
>    [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-glk6/igt@gem_eio@in-flight-suspend.html
> 
>   * igt@gem_exec_create@forked:
>     - shard-glk:          [FAIL][70] -> [FAIL][71] ([i915#1888])
>    [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-glk8/igt@gem_exec_create@forked.html
>    [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-glk2/igt@gem_exec_create@forked.html
>     - shard-hsw:          [FAIL][72] -> [FAIL][73] ([i915#1888])
>    [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-hsw8/igt@gem_exec_create@forked.html
>    [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-hsw6/igt@gem_exec_create@forked.html
> 
>   * igt@i915_pm_dc@dc3co-vpb-simulation:
>     - shard-skl:          [SKIP][74] ([fdo#109271] / [i915#658]) -> [INCOMPLETE][75] ([i915#198])
>    [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl9/igt@i915_pm_dc@dc3co-vpb-simulation.html
>    [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl9/igt@i915_pm_dc@dc3co-vpb-simulation.html
> 
>   * igt@kms_dp_dsc@basic-dsc-enable-edp:
>     - shard-iclb:         [SKIP][76] ([fdo#109349]) -> [DMESG-WARN][77] ([i915#1226])
>    [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html
>    [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
> 
>   * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
>     - shard-tglb:         [DMESG-WARN][78] ([i915#2411]) -> [DMESG-WARN][79] ([i915#1982] / [i915#2411])
>    [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
>    [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-tglb2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> 
>   * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
>     - shard-tglb:         [INCOMPLETE][80] ([i915#1436] / [i915#456]) -> [INCOMPLETE][81] ([i915#1436])
>    [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-tglb1/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
>    [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-tglb5/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
> 
>   * igt@runner@aborted:
>     - shard-skl:          ([FAIL][82], [FAIL][83]) ([i915#1436] / [i915#1611] / [i915#2439] / [i915#483]) -> [FAIL][84] ([i915#1611] / [i915#2439])
>    [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl5/igt@runner@aborted.html
>    [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9312/shard-skl6/igt@runner@aborted.html
>    [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/shard-skl10/igt@runner@aborted.html
> 
>   
>   {name}: This element is suppressed. This means it is ignored when computing
>           the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>   [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
>   [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
>   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
>   [i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
>   [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
>   [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
>   [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
>   [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
>   [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
>   [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
>   [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
>   [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
>   [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
>   [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
>   [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
>   [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
>   [i915#2377]: https://gitlab.freedesktop.org/drm/intel/issues/2377
>   [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
>   [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
>   [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
>   [i915#2635]: https://gitlab.freedesktop.org/drm/intel/issues/2635
>   [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
>   [i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
>   [i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51
>   [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
>   [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
>   [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
>   [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
> 
> 
> Participating hosts (11 -> 11)
> ------------------------------
> 
>   No changes in participating hosts
> 
> 
> Build changes
> -------------
> 
>   * Linux: CI_DRM_9312 -> Patchwork_18891
> 
>   CI-20190529: 20190529
>   CI_DRM_9312: 88b74d59a27aa168f7cd2dec199c33ee71fe8bb0 @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_5847: 8cffaebec5228a5042cc6928ac582a0589e2de3e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_18891: 8be57882b8f8fe53a333e8d9cf72d779096b0cd1 @ git://anongit.freedesktop.org/gfx-ci/linux
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18891/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread

end of thread, other threads:[~2020-11-12  6:27 UTC | newest]

Thread overview: 32+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-11-02 21:19 [Intel-gfx] [PATCH v5 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Manasi Navare
2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 2/6] drm/i915: Move encoder->get_config to a new function Manasi Navare
2020-11-05 15:15   ` Ville Syrjälä
2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 3/6] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split Manasi Navare
2020-11-02 23:04   ` [Intel-gfx] [PATCH v6 " Manasi Navare
2020-11-05 15:13     ` Ville Syrjälä
2020-11-05 16:03       ` Navare, Manasi
2020-11-05 16:15         ` Ville Syrjälä
2020-11-05 18:59           ` Navare, Manasi
2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 4/6] drm/i915: Pass intel_atomic_state instead of drm_atomic_state Manasi Navare
2020-11-05 15:14   ` Ville Syrjälä
2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 5/6] drm/i915/dp: Prep for bigjoiner atomic check Manasi Navare
2020-11-05 15:21   ` Ville Syrjälä
2020-11-05 15:23     ` Ville Syrjälä
2020-11-05 16:09       ` Navare, Manasi
2020-11-05 16:16         ` Ville Syrjälä
2020-11-02 21:19 ` [Intel-gfx] [PATCH v5 6/6] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3 Manasi Navare
2020-11-03 16:00   ` [Intel-gfx] [PATCH v6 " Manasi Navare
2020-11-05 16:11     ` Navare, Manasi
2020-11-05 16:27     ` Ville Syrjälä
2020-11-02 21:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes Patchwork
2020-11-02 22:04 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-11-02 23:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev2) Patchwork
2020-11-02 23:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-03  7:25 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-11-03 16:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev3) Patchwork
2020-11-03 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-03 22:52 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-11-12  0:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes (rev4) Patchwork
2020-11-12  1:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-12  4:09 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-11-12  6:29   ` Navare, Manasi

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