Re: [Intel-gfx] [PATCH 1/4] drm/i915: Introduce intel_dpll_get_hw_state()

[Imre Deak <imre.deak@intel.com>]

On Tue, Nov 10, 2020 at 01:12:36AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add a wrapper for the pll .get_hw_state() vfunc. Makes life
> a bit less miserable when you don't have to worry where the
> function pointer is stored.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

There's also assert_shared_dpll().

> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 14 +++++++------
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 ++++++++++++++++---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  3 +++
>  3 files changed, 28 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2729c852c668..a7c4cd7a8a31 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10927,6 +10927,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
>  	if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
>  		struct intel_shared_dpll *pll;
>  		enum intel_dpll_id pll_id;
> +		bool pll_active;
>  
>  		pipe_config->has_pch_encoder = true;
>  
> @@ -10954,8 +10955,9 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
>  			intel_get_shared_dpll_by_id(dev_priv, pll_id);
>  		pll = pipe_config->shared_dpll;
>  
> -		drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
> -						 &pipe_config->dpll_hw_state));
> +		pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> +						     &pipe_config->dpll_hw_state);
> +		drm_WARN_ON(dev, !pll_active);
>  
>  		tmp = pipe_config->dpll_hw_state.dpll;
>  		pipe_config->pixel_multiplier =
> @@ -11346,9 +11348,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
>  
>  	pll = pipe_config->shared_dpll;
>  	if (pll) {
> -		drm_WARN_ON(&dev_priv->drm,
> -			    !pll->info->funcs->get_hw_state(dev_priv, pll,
> -						&pipe_config->dpll_hw_state));
> +		bool pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> +							  &pipe_config->dpll_hw_state);
> +		drm_WARN_ON(&dev_priv->drm, !pll_active);
>  	}
>  
>  	/*
> @@ -14587,7 +14589,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
>  
>  	drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
>  
> -	active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
> +	active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
>  
>  	if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
>  		I915_STATE_WARN(!pll->on && pll->active_mask,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index a95e6a2ac698..1604c20bac33 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -141,7 +141,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
>  		     "asserting DPLL %s with no DPLL\n", onoff(state)))
>  		return;
>  
> -	cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state);
> +	cur_state = intel_dpll_get_hw_state(dev_priv, pll, &hw_state);
>  	I915_STATE_WARN(cur_state != state,
>  	     "%s assertion failure (expected %s, current %s)\n",
>  			pll->info->name, onoff(state), onoff(cur_state));
> @@ -4527,13 +4527,27 @@ int intel_dpll_get_freq(struct drm_i915_private *i915,
>  	return pll->info->funcs->get_freq(i915, pll);
>  }
>  
> +/**
> + * intel_dpll_get_hw_state - readout the DPLL's hardware state
> + * @i915: i915 device
> + * @pll: DPLL for which to calculate the output frequency
> + * @hw_state: DPLL's hardware state
> + *
> + * Read out @pll's hardware state into @hw_state.
> + */
> +bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
> +			     struct intel_shared_dpll *pll,
> +			     struct intel_dpll_hw_state *hw_state)
> +{
> +	return pll->info->funcs->get_hw_state(i915, pll, hw_state);
> +}
> +
>  static void readout_dpll_hw_state(struct drm_i915_private *i915,
>  				  struct intel_shared_dpll *pll)
>  {
>  	struct intel_crtc *crtc;
>  
> -	pll->on = pll->info->funcs->get_hw_state(i915, pll,
> -						 &pll->state.hw_state);
> +	pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
>  
>  	if (IS_JSL_EHL(i915) && pll->on &&
>  	    pll->info->id == DPLL_ID_EHL_DPLL4) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 205542fb8dc7..4357f92eafd6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -400,6 +400,9 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
>  			      struct intel_encoder *encoder);
>  int intel_dpll_get_freq(struct drm_i915_private *i915,
>  			const struct intel_shared_dpll *pll);
> +bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
> +			     struct intel_shared_dpll *pll,
> +			     struct intel_dpll_hw_state *hw_state);
>  void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
>  void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
>  void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> -- 
> 2.26.2
> 
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