From: Ramalingam C <ramalingam.c@intel.com>
To: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: jani.nikula@intel.com, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org, seanpaul@chromium.org
Subject: Re: [Intel-gfx] [PATCH v5 13/17] drm/i915/hdcp: MST streams support in hdcp port_data
Date: Tue, 24 Nov 2020 22:19:57 +0530 [thread overview]
Message-ID: <20201124164957.GB25919@intel.com> (raw)
In-Reply-To: <20201111062051.11529-14-anshuman.gupta@intel.com>
On 2020-11-11 at 11:50:47 +0530, Anshuman Gupta wrote:
> Add support for multiple mst stream in hdcp port data
> which will be used by RepeaterAuthStreamManage msg and
> HDCP 2.2 security f/w for m' validation.
>
> Security f/w doesn't have any provision to mark the
> stream_type for each stream separately, it just take
> single input of stream_type while authentiating the
> port. So driver mark each stream_type with common
> highest supported content type for all streams in
> DP MST Topology.
>
> Security f/w supports RepeaterAuthStreamManage msg and m'
> validation only once during port authentication and encryption.
Could we make a note in commit msg that we need to support content type per stream
when fw supports it?
>
> v2:
> - Init the hdcp port data k for HDMI/DP SST stream.
> v3:
> - Cosmetic changes. [Uma]
> v4:
> - 's/port_auth/hdcp_port_auth'. [Ram]
> - Commit log improvement.
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 4 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++++++++++++++---
> 2 files changed, 92 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6e597f6aafe8..b93ecf4f21e3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1445,10 +1445,12 @@ struct intel_digital_port {
> enum phy_fia tc_phy_fia;
> u8 tc_phy_fia_idx;
>
> - /* protects num_hdcp_streams reference count, port_data */
> + /* protects num_hdcp_streams reference count, port_data and port_auth */
Either correct the variable names or refer it as "hdcp related
variables"
> struct mutex hdcp_mutex;
> /* the number of pipes using HDCP signalling out of this port */
> unsigned int num_hdcp_streams;
> + /* port HDCP auth status */
> + bool hdcp_auth_status;
> /* HDCP port data need to pass to security f/w */
> struct hdcp_port_data hdcp_port_data;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 829176df89e7..6a48110c7cd7 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -26,6 +26,64 @@
> #define KEY_LOAD_TRIES 5
> #define HDCP2_LC_RETRY_CNT 3
>
> +static int intel_conn_to_vcpi(struct intel_connector *connector)
> +{
> + /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> + return connector->port ? connector->port->vcpi.vcpi : 0;
> +}
> +
Lets add a comment about policy on content type selection and why. And
mention that ideally we should be able to support different content type
for different streams.
> +static int
> +intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
> +{
> + struct drm_connector_list_iter conn_iter;
> + struct intel_digital_port *conn_dig_port;
> + struct intel_connector *connector;
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct hdcp_port_data *data = &dig_port->hdcp_port_data;
> + bool enforce_type0 = false;
> + int k;
> +
> + if (dig_port->hdcp_auth_status)
> + return 0;
> +
> + drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> + for_each_intel_connector_iter(connector, &conn_iter) {
> + if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
> + continue;
> +
> + conn_dig_port = intel_attached_dig_port(connector);
> + if (conn_dig_port != dig_port)
> + continue;
> +
> + if (connector->base.status == connector_status_disconnected)
> + continue;
> +
> + if (!enforce_type0 && !intel_hdcp2_capable(connector))
> + enforce_type0 = true;
> +
> + data->streams[data->k].stream_id = intel_conn_to_vcpi(connector);
> + data->k++;
> +
> + /* if there is only one active stream */
> + if (dig_port->dp.active_mst_links <= 1)
> + break;
> + }
> + drm_connector_list_iter_end(&conn_iter);
> +
> + if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k == 0))
> + return -EINVAL;
> +
> + /*
> + * Apply common protection level across all streams in DP MST Topology.
> + * Use highest supported content type for all streams in DP MST Topology.
> + */
> + for (k = 0; k < data->k; k++)
> + data->streams[k].stream_type =
> + enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1;
> +
> + return 0;
> +}
> +
> static
> bool intel_hdcp_is_ksv_valid(u8 *ksv)
> {
> @@ -1476,13 +1534,14 @@ static
> int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct hdcp_port_data *data = &dig_port->hdcp_port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> union {
> struct hdcp2_rep_stream_manage stream_manage;
> struct hdcp2_rep_stream_ready stream_ready;
> } msgs;
> const struct intel_hdcp_shim *shim = hdcp->shim;
> - int ret;
> + int ret, streams_size_delta, i;
>
> if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
> return -ERANGE;
> @@ -1491,16 +1550,18 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
> drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
>
> - /* K no of streams is fixed as 1. Stored as big-endian. */
> - msgs.stream_manage.k = cpu_to_be16(1);
> + msgs.stream_manage.k = cpu_to_be16(data->k);
>
> - /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> - msgs.stream_manage.streams[0].stream_id = 0;
> - msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
> + for (i = 0; i < data->k; i++) {
> + msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id;
> + msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type;
> + }
>
> + streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) *
> + sizeof(struct hdcp2_streamid_type);
> /* Send it to Repeater */
> ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
> - sizeof(msgs.stream_manage));
> + sizeof(msgs.stream_manage) - streams_size_delta);
> if (ret < 0)
> goto out;
>
> @@ -1509,8 +1570,7 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> if (ret < 0)
> goto out;
>
> - dig_port->hdcp_port_data.seq_num_m = hdcp->seq_num_m;
> - dig_port->hdcp_port_data.streams[0].stream_type = hdcp->content_type;
> + data->seq_num_m = hdcp->seq_num_m;
>
> ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
>
> @@ -1671,6 +1731,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
> port),
> LINK_ENCRYPTION_STATUS,
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
> + dig_port->hdcp_auth_status = true;
>
> return ret;
> }
> @@ -1745,11 +1806,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> {
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> - struct hdcp_port_data *data = &dig_port->hdcp_port_data;
> - struct intel_hdcp *hdcp = &connector->hdcp;
> - int ret, i, tries = 3;
> + int ret = 0, i, tries = 3;
>
> - for (i = 0; i < tries; i++) {
> + for (i = 0; i < tries && !dig_port->hdcp_auth_status; i++) {
> ret = hdcp2_authenticate_sink(connector);
> if (!ret) {
> ret = hdcp2_propagate_stream_management_info(connector);
> @@ -1759,7 +1818,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> ret);
> break;
> }
> - data->streams[0].stream_type = hdcp->content_type;
> +
> ret = hdcp2_authenticate_port(connector);
> if (!ret)
> break;
> @@ -1794,7 +1853,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
>
> static int _intel_hdcp2_enable(struct intel_connector *connector)
> {
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->hdcp_port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> int ret;
>
> @@ -1802,6 +1863,16 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
> connector->base.name, connector->base.base.id,
> hdcp->content_type);
>
> + /* Stream which requires encryption */
> + if (!intel_encoder_is_mst(intel_attached_encoder(connector))) {
> + data->k = 1;
> + data->streams[0].stream_type = hdcp->content_type;
> + } else {
> + ret = intel_hdcp_required_content_stream(dig_port);
> + if (ret)
> + return ret;
> + }
> +
> ret = hdcp2_authenticate_and_encrypt(connector);
> if (ret) {
> drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",
> @@ -1819,7 +1890,9 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
>
> static int _intel_hdcp2_disable(struct intel_connector *connector)
> {
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->hdcp_port_data;
> int ret;
>
> drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
> @@ -1831,6 +1904,8 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
> drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
>
> connector->hdcp.hdcp2_encrypted = false;
> + dig_port->hdcp_auth_status = false;
> + data->k = 0;
>
> return ret;
> }
With these comments addressed LGTM.
Ram
> --
> 2.26.2
>
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next prev parent reply other threads:[~2020-11-24 16:49 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-11 6:20 [Intel-gfx] [PATCH v5 00/17] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 01/17] drm/i915/hdcp: Update CP property in update_pipe Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 02/17] drm/i915/hdcp: Get conn while content_type changed Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 03/17] drm/i915/hotplug: Handle CP_IRQ for DP-MST Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 04/17] drm/i915/hdcp: DP MST transcoder for link and stream Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 05/17] drm/i915/hdcp: Move HDCP enc status timeout to header Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 06/17] drm/i915/hdcp: HDCP stream encryption support Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 07/17] drm/i915/hdcp: Enable HDCP 1.4 stream encryption Anshuman Gupta
2020-11-24 14:14 ` Ramalingam C
2020-11-24 15:05 ` Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 08/17] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support Anshuman Gupta
2020-11-24 14:20 ` Ramalingam C
2020-11-24 15:02 ` Anshuman Gupta
2020-11-24 16:17 ` Ramalingam C
2020-11-24 16:05 ` Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 09/17] drm/i915/hdcp: Pass dig_port to intel_hdcp_init Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 10/17] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 11/17] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 12/17] drm/hdcp: Max MST content streams Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 13/17] drm/i915/hdcp: MST streams support in hdcp port_data Anshuman Gupta
2020-11-24 16:49 ` Ramalingam C [this message]
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 14/17] drm/i915/hdcp: Pass connector to check_2_2_link Anshuman Gupta
2020-11-24 17:03 ` Ramalingam C
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 15/17] drm/i915/hdcp: Add HDCP 2.2 stream register Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 16/17] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Anshuman Gupta
2020-11-11 6:20 ` [Intel-gfx] [PATCH v5 17/17] drm/i915/hdcp: Enable HDCP 2.2 MST support Anshuman Gupta
2020-11-11 15:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev4) Patchwork
2020-11-11 16:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-11 18:16 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-11-24 10:57 ` [Intel-gfx] [PATCH v5 00/17] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support Karthik B S
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