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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Uma Shankar <uma.shankar@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [v11 01/13] drm/i915/display: Add HDR Capability detection for LSPCON
Date: Thu, 26 Nov 2020 18:26:22 +0200	[thread overview]
Message-ID: <20201126162622.GE6112@intel.com> (raw)
In-Reply-To: <20201126081445.29759-2-uma.shankar@intel.com>

On Thu, Nov 26, 2020 at 01:44:33PM +0530, Uma Shankar wrote:
> LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES
> DPCD register. LSPCON implementations capable of supporting
> HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch
> reads the same, detects the HDR capability and adds this to
> intel_lspcon struct.
> 
> v2: Addressed Jani Nikula's review comment and fixed the HDR
>     capability detection logic
> 
> v3: Deferred HDR detection from lspcon_init (Ville)
> 
> v4: Addressed Ville's minor review comments, added his RB.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Reviewed-by: Ville Syrjä <ville.syrjala@linux.intel.com>

Wrong name

> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_lspcon.c   | 27 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_lspcon.h   |  1 +
>  3 files changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ce82d654d0f2..5a949218dd3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1450,6 +1450,7 @@ enum lspcon_vendor {
>  
>  struct intel_lspcon {
>  	bool active;
> +	bool hdr_supported;
>  	enum drm_lspcon_mode mode;
>  	enum lspcon_vendor vendor;
>  };
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index e37d45e531df..3065727015a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -35,6 +35,8 @@
>  #define LSPCON_VENDOR_PARADE_OUI 0x001CF8
>  #define LSPCON_VENDOR_MCA_OUI 0x0060AD
>  
> +#define DPCD_MCA_LSPCON_HDR_STATUS	0x70003
> +
>  /* AUX addresses to write MCA AVI IF */
>  #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
>  #define LSPCON_MCA_AVI_IF_CTRL 0x5DF
> @@ -104,6 +106,31 @@ static bool lspcon_detect_vendor(struct intel_lspcon *lspcon)
>  	return true;
>  }
>  
> +void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
> +{
> +	struct intel_digital_port *dig_port =
> +		container_of(lspcon, struct intel_digital_port, lspcon);
> +	struct drm_device *dev = dig_port->base.base.dev;
> +	struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
> +	u8 hdr_caps;
> +	int ret;
> +
> +	/* Enable HDR for MCA based LSPCON devices */
> +	if (lspcon->vendor == LSPCON_VENDOR_MCA)
> +		ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS,
> +				       &hdr_caps, 1);
> +	else
> +		return;
> +
> +	if (ret < 0) {
> +		drm_dbg_kms(dev, "HDR capability detection failed\n");
> +		lspcon->hdr_supported = false;
> +	} else if (hdr_caps & 0x1) {
> +		drm_dbg_kms(dev, "LSPCON capable of HDR\n");
> +		lspcon->hdr_supported = true;
> +	}
> +}
> +
>  static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon)
>  {
>  	enum drm_lspcon_mode current_mode;
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h
> index b03dcb7076d8..a19b3564c635 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.h
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
> @@ -15,6 +15,7 @@ struct intel_digital_port;
>  struct intel_encoder;
>  struct intel_lspcon;
>  
> +void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon);
>  void lspcon_resume(struct intel_digital_port *dig_port);
>  void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
>  void lspcon_write_infoframe(struct intel_encoder *encoder,
> -- 
> 2.26.2

-- 
Ville Syrjälä
Intel
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Intel-gfx@lists.freedesktop.org
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  reply	other threads:[~2020-11-26 16:26 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-26  8:14 [Intel-gfx] [v11 00/13] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
2020-11-26  8:14 ` [Intel-gfx] [v11 01/13] drm/i915/display: Add HDR Capability detection for LSPCON Uma Shankar
2020-11-26 16:26   ` Ville Syrjälä [this message]
2020-11-26 20:10     ` Shankar, Uma
2020-11-26  8:14 ` [Intel-gfx] [v11 02/13] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Uma Shankar
2020-11-26  8:14 ` [Intel-gfx] [v11 03/13] drm/i915/display: Attach HDR property for capable Gen9 devices Uma Shankar
2020-11-26  8:14 ` [Intel-gfx] [v11 04/13] drm/i915/display: Enable quantization range for HDR on LSPCON devices Uma Shankar
2020-11-26 16:27   ` Ville Syrjälä
2020-11-26  8:14 ` [Intel-gfx] [v11 05/13] drm/i915/display: Add a WARN for invalid output range and format Uma Shankar
2020-11-26 16:27   ` Ville Syrjälä
2020-11-26  8:14 ` [Intel-gfx] [v11 06/13] drm/i915/display: Attach content type property for LSPCON Uma Shankar
2020-11-26 16:28   ` Ville Syrjälä
2020-11-26  8:14 ` [Intel-gfx] [v11 07/13] i915/display: Enable BT2020 for HDR on LSPCON devices Uma Shankar
2020-11-26 17:13   ` Ville Syrjälä
2020-11-26 20:23     ` Shankar, Uma
2020-11-26  8:14 ` [Intel-gfx] [v11 08/13] drm/i915/display: Enable HDR for Parade based lspcon Uma Shankar
2020-11-26  8:14 ` [Intel-gfx] [v11 09/13] drm/i915/display: Implement infoframes readback for LSPCON Uma Shankar
2020-11-26 16:32   ` Ville Syrjälä
2020-11-26 17:44     ` Ville Syrjälä
2020-11-26 20:11       ` Shankar, Uma
2020-11-26  8:14 ` [Intel-gfx] [v11 10/13] drm/i915/display: Implement DRM infoframe read " Uma Shankar
2020-11-26  8:14 ` [Intel-gfx] [v11 11/13] drm/i915/lspcon: Create separate infoframe_enabled helper Uma Shankar
2020-11-26  8:14 ` [Intel-gfx] [v11 12/13] drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks Uma Shankar
2020-11-26  8:14 ` [Intel-gfx] [v11 13/13] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON Uma Shankar
2020-11-26  9:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev11) Patchwork
2020-11-26  9:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-26 10:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-26 12:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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