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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Uma Shankar <uma.shankar@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [v11 09/13] drm/i915/display: Implement infoframes readback for LSPCON
Date: Thu, 26 Nov 2020 18:32:02 +0200	[thread overview]
Message-ID: <20201126163202.GI6112@intel.com> (raw)
In-Reply-To: <20201126081445.29759-10-uma.shankar@intel.com>

On Thu, Nov 26, 2020 at 01:44:41PM +0530, Uma Shankar wrote:
> Implemented Infoframes enabled readback for LSPCON devices.
> This will help align the implementation with state readback
> infrastructure.
> 
> v2: Added proper bitmask of enabled infoframes as per Ville's
> recommendation.
> 
> v3: Added pcon specific infoframe types instead of using the HSW
> one's, as recommended by Ville.
> 
> v4: Addressed Ville's review comment by adding HDMI infoframe
> versions directly instead of DIP wrappers.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_lspcon.c | 57 ++++++++++++++++++++-
>  1 file changed, 55 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index 1d3dffade168..4f3c4943e918 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -574,11 +574,64 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
>  				  buf, ret);
>  }
>  
> +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux)
> +{
> +	int ret;
> +	u32 val = 0;
> +	u16 reg = LSPCON_MCA_AVI_IF_CTRL;
> +
> +	ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> +	if (ret < 0) {
> +		DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> +		return false;
> +	}
> +
> +	return val & LSPCON_MCA_AVI_IF_KICKOFF;
> +}
> +
> +static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux)
> +{
> +	int ret;
> +	u32 val = 0;
> +	u16 reg = LSPCON_PARADE_AVI_IF_CTRL;
> +
> +	ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> +	if (ret < 0) {
> +		DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> +		return false;
> +	}
> +
> +	return val & LSPCON_PARADE_AVI_IF_KICKOFF;
> +}
> +
>  u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
>  			      const struct intel_crtc_state *pipe_config)
>  {
> -	/* FIXME actually read this from the hw */
> -	return 0;
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	bool infoframes_enabled;
> +	u32 val = 0;
> +	u32 mask, tmp;
> +
> +	if (lspcon->vendor == LSPCON_VENDOR_MCA)
> +		infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux);
> +	else
> +		infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux);
> +
> +	if (infoframes_enabled)
> +		val |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
> +
> +	if (lspcon->hdr_supported) {
> +		tmp = intel_de_read(dev_priv,
> +				    HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
> +		mask = VIDEO_DIP_ENABLE_GMP_HSW;
> +
> +		if (tmp & mask)
> +			val |= intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
> +	}
> +
> +	return val;
>  }

This seem broken until patch 10 which avoids the
remapping from DIP bits to the index. With some reordering
of the patches this seems good.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>  
>  void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon)
> -- 
> 2.26.2

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2020-11-26 16:32 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-26  8:14 [Intel-gfx] [v11 00/13] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
2020-11-26  8:14 ` [Intel-gfx] [v11 01/13] drm/i915/display: Add HDR Capability detection for LSPCON Uma Shankar
2020-11-26 16:26   ` Ville Syrjälä
2020-11-26 20:10     ` Shankar, Uma
2020-11-26  8:14 ` [Intel-gfx] [v11 02/13] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Uma Shankar
2020-11-26  8:14 ` [Intel-gfx] [v11 03/13] drm/i915/display: Attach HDR property for capable Gen9 devices Uma Shankar
2020-11-26  8:14 ` [Intel-gfx] [v11 04/13] drm/i915/display: Enable quantization range for HDR on LSPCON devices Uma Shankar
2020-11-26 16:27   ` Ville Syrjälä
2020-11-26  8:14 ` [Intel-gfx] [v11 05/13] drm/i915/display: Add a WARN for invalid output range and format Uma Shankar
2020-11-26 16:27   ` Ville Syrjälä
2020-11-26  8:14 ` [Intel-gfx] [v11 06/13] drm/i915/display: Attach content type property for LSPCON Uma Shankar
2020-11-26 16:28   ` Ville Syrjälä
2020-11-26  8:14 ` [Intel-gfx] [v11 07/13] i915/display: Enable BT2020 for HDR on LSPCON devices Uma Shankar
2020-11-26 17:13   ` Ville Syrjälä
2020-11-26 20:23     ` Shankar, Uma
2020-11-26  8:14 ` [Intel-gfx] [v11 08/13] drm/i915/display: Enable HDR for Parade based lspcon Uma Shankar
2020-11-26  8:14 ` [Intel-gfx] [v11 09/13] drm/i915/display: Implement infoframes readback for LSPCON Uma Shankar
2020-11-26 16:32   ` Ville Syrjälä [this message]
2020-11-26 17:44     ` Ville Syrjälä
2020-11-26 20:11       ` Shankar, Uma
2020-11-26  8:14 ` [Intel-gfx] [v11 10/13] drm/i915/display: Implement DRM infoframe read " Uma Shankar
2020-11-26  8:14 ` [Intel-gfx] [v11 11/13] drm/i915/lspcon: Create separate infoframe_enabled helper Uma Shankar
2020-11-26  8:14 ` [Intel-gfx] [v11 12/13] drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks Uma Shankar
2020-11-26  8:14 ` [Intel-gfx] [v11 13/13] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON Uma Shankar
2020-11-26  9:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev11) Patchwork
2020-11-26  9:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-26 10:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-26 12:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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