From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [v4 2/2] Revert "drm/i915/display/fbc: Disable fbc by default on TGL"
Date: Tue, 1 Dec 2020 20:00:42 +0530 [thread overview]
Message-ID: <20201201143042.22188-3-uma.shankar@intel.com> (raw)
In-Reply-To: <20201201143042.22188-1-uma.shankar@intel.com>
FBC can be re-enabled on TGL with WA of keeping it disabled
while PSR2 is enabled.
This reverts commit 2982ded2ff5ce0cf1a49bc39a526da182782b664.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index ff2f2c00a10e..9ac778f425f0 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1462,13 +1462,6 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
if (!HAS_FBC(dev_priv))
return 0;
- /*
- * Fbc is causing random underruns in CI execution on TGL platforms.
- * Disabling the same while the problem is being debugged and analyzed.
- */
- if (IS_TIGERLAKE(dev_priv))
- return 0;
-
if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
return 1;
--
2.26.2
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next prev parent reply other threads:[~2020-12-01 13:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-01 14:30 [Intel-gfx] [v4 0/2] Re-enable FBC on TGL Uma Shankar
2020-12-01 14:30 ` [Intel-gfx] [v4 1/2] drm/i915/display/tgl: Disable FBC with PSR2 Uma Shankar
2020-12-01 15:51 ` Souza, Jose
2020-12-01 15:55 ` Souza, Jose
2020-12-01 16:00 ` Shankar, Uma
2020-12-01 14:30 ` Uma Shankar [this message]
2020-12-01 14:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Re-enable FBC on TGL (rev4) Patchwork
2020-12-01 15:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-12-01 18:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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