From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Calculate min_ddb_alloc for trans_wm
Date: Fri, 5 Mar 2021 17:36:08 +0200 [thread overview]
Message-ID: <20210305153610.12177-5-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210305153610.12177-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's make all the "do we have enough DDB for this WM level?"
checks use min_ddb_alloc. To achieve that we need to populate
this for the transition watermarks as well.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 36601e0a5073..38a6feced74f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4986,13 +4986,13 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
- if (wm->trans_wm.plane_res_b >= total[plane_id])
+ if (wm->trans_wm.min_ddb_alloc > total[plane_id])
memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
if (wm->sagv.wm0.min_ddb_alloc > total[plane_id])
memset(&wm->sagv.wm0, 0, sizeof(wm->sagv.wm0));
- if (wm->sagv.trans_wm.plane_res_b >= total[plane_id])
+ if (wm->sagv.trans_wm.min_ddb_alloc > total[plane_id])
memset(&wm->sagv.trans_wm, 0, sizeof(wm->sagv.trans_wm));
}
@@ -5404,13 +5404,15 @@ static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
} else {
res_blocks = wm0_sel_res_b + trans_offset_b;
}
+ res_blocks++;
/*
* Just assume we can enable the transition watermark. After
* computing the DDB we'll come back and disable it if that
* assumption turns out to be false.
*/
- trans_wm->plane_res_b = res_blocks + 1;
+ trans_wm->plane_res_b = res_blocks;
+ trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, res_blocks + 1);
trans_wm->plane_en = true;
}
--
2.26.2
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next prev parent reply other threads:[~2021-03-05 15:36 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-05 15:36 [Intel-gfx] [PATCH 0/6] drm/i915: More SAGV related fixes/cleanups Ville Syrjala
2021-03-05 15:36 ` [Intel-gfx] [PATCH 1/6] drm/i915: Fix enabled_planes bitmask Ville Syrjala
2021-03-19 21:17 ` Navare, Manasi
2021-03-19 21:20 ` Ville Syrjälä
2021-03-19 21:30 ` Navare, Manasi
2021-03-05 15:36 ` [Intel-gfx] [PATCH 2/6] drm/i915: Tighten SAGV constraint for pre-tgl Ville Syrjala
2021-03-11 14:36 ` Lisovskiy, Stanislav
2021-03-11 15:28 ` Ville Syrjälä
2021-03-12 12:12 ` Lisovskiy, Stanislav
2021-03-05 15:36 ` [Intel-gfx] [PATCH 3/6] drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_b Ville Syrjala
2021-03-12 12:13 ` Lisovskiy, Stanislav
2021-03-05 15:36 ` Ville Syrjala [this message]
2021-03-12 12:14 ` [Intel-gfx] [PATCH 4/6] drm/i915: Calculate min_ddb_alloc for trans_wm Lisovskiy, Stanislav
2021-03-05 15:36 ` [Intel-gfx] [PATCH 5/6] drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level() Ville Syrjala
2021-03-12 12:25 ` Lisovskiy, Stanislav
2021-03-05 15:36 ` [Intel-gfx] [PATCH 6/6] drm/i915: s/plane_res_b/blocks/ etc Ville Syrjala
2021-03-11 14:26 ` Lisovskiy, Stanislav
2021-03-12 12:45 ` Lisovskiy, Stanislav
2021-03-05 16:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: More SAGV related fixes/cleanups Patchwork
2021-03-05 16:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-03-05 20:11 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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