Re: [Intel-gfx] [PATCH 2/6] drm/i915: Tighten SAGV constraint for pre-tgl

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Mar 11, 2021 at 04:36:05PM +0200, Lisovskiy, Stanislav wrote:
> On Fri, Mar 05, 2021 at 05:36:06PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Say we have two planes enabled with watermarks configured
> > as follows:
> > plane A: wm0=enabled/can_sagv=false, wm1=enabled/can_sagv=true
> > plane B: wm0=enabled/can_sagv=true,  wm1=disabled
> 
> Was thinking about this, always thought its not possible, i.e
> wm1 kinda requires more resources, so if we can do wm1, should
> always be able to do wm0..
> 
> > 
> > This is possible since the latency we use to calculate
> > can_sagv may not be the same for both planes due to
> > skl_needs_memory_bw_wa().
> 
> The current code, which I see in internal at least looks like this:
> 
> /*
>  * FIXME: We still don't have the proper code detect if we need to apply the WA,
>  * so assume we'll always need it in order to avoid underruns.
>  */
> static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
> {
>       return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> }
> 
> i.e I think it will return same latency for all planes.
> 
> Or am I missing something?..

We do stuff like 
if (skl_needs_memory_bw_wa(dev_priv) && wp->x_tiled)
	latency += 15;
so different latencies for different tilings.

Also the fact that eg. Y vs. X/linear do the method1 vs. method2
selection differently could mean we get different set of wm levels
even w/o any latency adjustments. Or at least it's impossible for
me to see from the code that it couldn't happen.

-- 
Ville Syrjälä
Intel
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