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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: [Intel-gfx] [PATCH v2 3/7] drm/i915: Relocate intel_dp_program_link_training_pattern()
Date: Thu, 18 Mar 2021 18:10:11 +0200	[thread overview]
Message-ID: <20210318161015.22070-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210318161015.22070-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_dp_program_link_training_pattern() clearly belongs in
intel_dp_link_training.c. Make it so.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c       | 33 -------------------
 drivers/gpu/drm/i915/display/intel_dp.h       |  4 ---
 .../drm/i915/display/intel_dp_link_training.c | 33 +++++++++++++++++++
 .../drm/i915/display/intel_dp_link_training.h |  3 ++
 4 files changed, 36 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0ce96bd87a49..415732b80108 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3386,39 +3386,6 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
 }
 
-static char dp_training_pattern_name(u8 train_pat)
-{
-	switch (train_pat) {
-	case DP_TRAINING_PATTERN_1:
-	case DP_TRAINING_PATTERN_2:
-	case DP_TRAINING_PATTERN_3:
-		return '0' + train_pat;
-	case DP_TRAINING_PATTERN_4:
-		return '4';
-	default:
-		MISSING_CASE(train_pat);
-		return '?';
-	}
-}
-
-void
-intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
-				       const struct intel_crtc_state *crtc_state,
-				       u8 dp_train_pat)
-{
-	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
-
-	if (train_pat != DP_TRAINING_PATTERN_DISABLE)
-		drm_dbg_kms(&dev_priv->drm,
-			    "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
-			    encoder->base.base.id, encoder->base.name,
-			    dp_training_pattern_name(train_pat));
-
-	intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
-}
-
 static void
 intel_dp_link_down(struct intel_encoder *encoder,
 		   const struct intel_crtc_state *old_crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index d80839139bfb..d673cba16835 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -87,10 +87,6 @@ void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
 			  unsigned int frontbuffer_bits);
 
-void
-intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
-				       const struct intel_crtc_state *crtc_state,
-				       u8 dp_train_pat);
 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 			   u8 *link_bw, u8 *rate_select);
 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 19ba7c7cbaab..5a37b9da7652 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -329,6 +329,39 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
 	return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
 }
 
+static char dp_training_pattern_name(u8 train_pat)
+{
+	switch (train_pat) {
+	case DP_TRAINING_PATTERN_1:
+	case DP_TRAINING_PATTERN_2:
+	case DP_TRAINING_PATTERN_3:
+		return '0' + train_pat;
+	case DP_TRAINING_PATTERN_4:
+		return '4';
+	default:
+		MISSING_CASE(train_pat);
+		return '?';
+	}
+}
+
+void
+intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
+				       const struct intel_crtc_state *crtc_state,
+				       u8 dp_train_pat)
+{
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
+
+	if (train_pat != DP_TRAINING_PATTERN_DISABLE)
+		drm_dbg_kms(&dev_priv->drm,
+			    "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
+			    encoder->base.base.id, encoder->base.name,
+			    dp_training_pattern_name(train_pat));
+
+	intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
+}
+
 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
 				const struct intel_crtc_state *crtc_state,
 				enum drm_dp_phy dp_phy)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 6a1f76bd8c75..2aa6767c3a28 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -17,6 +17,9 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state,
 			       enum drm_dp_phy dp_phy,
 			       const u8 link_status[DP_LINK_STATUS_SIZE]);
+void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
+					    const struct intel_crtc_state *crtc_state,
+					    u8 dp_train_pat);
 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
 				const struct intel_crtc_state *crtc_state,
 				enum drm_dp_phy dp_phy);
-- 
2.26.2

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  parent reply	other threads:[~2021-03-18 16:10 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-18 16:10 [Intel-gfx] [PATCH v2 0/7] drm/i915: Shuffle DP code around Ville Syrjala
2021-03-18 16:10 ` [Intel-gfx] [PATCH v2 1/7] drm/i915: Remove dead TPS3->TPS2 fallback code Ville Syrjala
2021-03-18 16:10 ` [Intel-gfx] [PATCH v2 2/7] drm/i915: Remove dead signal level debugs Ville Syrjala
2021-03-18 16:10 ` Ville Syrjala [this message]
2021-03-18 16:10 ` [Intel-gfx] [PATCH v2 4/7] drm/i915: Split intel_ddi_encoder_reset() from intel_dp_encoder_reset() Ville Syrjala
2021-03-18 16:10 ` [Intel-gfx] [PATCH v2 5/7] drm/i915: Introduce g4x_dp.c Ville Syrjala
2021-03-18 16:10 ` [Intel-gfx] [PATCH v2 6/7] drm/i915: Introduce g4x_hdmi.c Ville Syrjala
2021-03-18 16:10 ` [Intel-gfx] [PATCH v2 7/7] drm/i915: Give g4x_{dp, hdmi}.c g4x_ namespace Ville Syrjala
2021-03-18 18:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Shuffle DP code around (rev2) Patchwork
2021-03-18 18:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-03-18 18:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-03-18 23:39 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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