From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [RFC 25/28] drm/i915: Use IS_GEN in intel_engine_cs.c
Date: Wed, 14 Apr 2021 12:50:25 +0100 [thread overview]
Message-ID: <20210414115028.168504-26-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <20210414115028.168504-1-tvrtko.ursulin@linux.intel.com>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 92 +++++++++++---------------
1 file changed, 38 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 32a1fee719a0..3f97e1491fad 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -156,36 +156,30 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
switch (class) {
case RENDER_CLASS:
- switch (INTEL_GEN(dev_priv)) {
- default:
- MISSING_CASE(INTEL_GEN(dev_priv));
- return DEFAULT_LR_CONTEXT_RENDER_SIZE;
- case 11:
+ if (IS_GEN(dev_priv, 11, GEN_FOREVER)) {
return GEN11_LR_CONTEXT_RENDER_SIZE;
- case 10:
+ } else if (IS_GEN(dev_priv, 10, GEN_FOREVER)) {
return GEN10_LR_CONTEXT_RENDER_SIZE;
- case 9:
+ } else if (IS_GEN(dev_priv, 9, GEN_FOREVER)) {
return GEN9_LR_CONTEXT_RENDER_SIZE;
- case 8:
+ } else if (IS_GEN(dev_priv, 8, GEN_FOREVER)) {
return GEN8_LR_CONTEXT_RENDER_SIZE;
- case 7:
+ } else if (IS_GEN(dev_priv, 7, GEN_FOREVER)) {
if (IS_HASWELL(dev_priv))
return HSW_CXT_TOTAL_SIZE;
cxt_size = I915_READ(GEN7_CXT_SIZE);
return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
- case 6:
+ } else if (IS_GEN(dev_priv, 6, GEN_FOREVER)) {
cxt_size = I915_READ(CXT_SIZE);
return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
PAGE_SIZE);
- case 5:
- case 4:
- case 3:
- case 2:
- /* For the special day when i810 gets merged. */
- case 1:
+ } else if (IS_GEN(dev_priv, 1, 5)) {
return 0;
+ } else {
+ MISSING_CASE(INTEL_GEN(dev_priv));
+ return DEFAULT_LR_CONTEXT_RENDER_SIZE;
}
break;
default:
@@ -781,47 +775,39 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
memset(instdone, 0, sizeof(*instdone));
- switch (INTEL_GEN(dev_priv)) {
- default:
+ if (IS_GEN7(dev_priv)) {
instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
- if (engine->id != RCS)
- break;
-
- instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
- instdone->sampler[slice][subslice] =
- read_subslice_reg(dev_priv, slice, subslice,
- GEN7_SAMPLER_INSTDONE);
- instdone->row[slice][subslice] =
- read_subslice_reg(dev_priv, slice, subslice,
- GEN7_ROW_INSTDONE);
+ if (engine->id == RCS) {
+ instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
+ instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE);
+ instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE);
}
- break;
- case 7:
- instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
-
- if (engine->id != RCS)
- break;
-
- instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
- instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE);
- instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE);
-
- break;
- case 6:
- case 5:
- case 4:
+ } else if (IS_GEN(dev_priv, 4, 6)) {
instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
if (engine->id == RCS)
/* HACK: Using the wrong struct member */
instdone->slice_common = I915_READ(GEN4_INSTDONE1);
- break;
- case 3:
- case 2:
+ } else if (IS_GEN(dev_priv, 2, 3)) {
instdone->instdone = I915_READ(GEN2_INSTDONE);
- break;
+ } else {
+ instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
+
+ if (engine->id == RCS) {
+ instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
+ for_each_instdone_slice_subslice(dev_priv, slice,
+ subslice) {
+ instdone->sampler[slice][subslice] =
+ read_subslice_reg(dev_priv, slice,
+ subslice,
+ GEN7_SAMPLER_INSTDONE);
+ instdone->row[slice][subslice] =
+ read_subslice_reg(dev_priv, slice,
+ subslice,
+ GEN7_ROW_INSTDONE);
+ }
+ }
}
}
@@ -1634,17 +1620,15 @@ void intel_engines_unpark(struct drm_i915_private *i915)
bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
{
- switch (INTEL_GEN(engine->i915)) {
- case 2:
+ if (IS_GEN2(engine->i915))
return false; /* uses physical not virtual addresses */
- case 3:
+ else if (IS_GEN3(engine->i915))
/* maybe only uses physical not virtual addresses */
return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
- case 6:
+ else if (IS_GEN6(engine->i915))
return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
- default:
+ else
return true;
- }
}
unsigned int intel_engines_has_context_isolation(struct drm_i915_private *i915)
--
2.27.0
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next prev parent reply other threads:[~2021-04-14 11:51 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-14 11:50 [Intel-gfx] [RFC 00/28] Old platform/gen kconfig options series Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 01/28] drm/i915: Make I830 platform support optional Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 02/28] drm/i915: Make I845G " Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 03/28] drm/i915: Make I85X " Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 04/28] drm/i915: Make I865G " Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 05/28] drm/i915: Make GEN2 " Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 06/28] drm/i915: Make Gen3 platforms " Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 07/28] drm/i915: Make Gen4 " Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 08/28] drm/i915: Make Ironlake/Gen5 " Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 09/28] drm/i915: Make Sandybridge/Gen6 " Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 10/28] drm/i915: Make Gen7/7.5 platform " Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 11/28] drm/i915: Make Gen8 " Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 12/28] drm/i915: Make Gen9 " Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 13/28] drm/i915: Make Gen10 " Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 14/28] drm/i915: Make Gen11 " Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 15/28] drm/i915: Simplify IS_GEN macros Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 16/28] drm/i915: Use INTEL_GEN everywhere Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 17/28] drm/i915: Favour IS_GENx Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 18/28] drm/i915: Use Gen Kconfig items in IS_GEN macro Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 19/28] drm/i915: Replace arithmetic INTEL_GEN checks with the " Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 20/28] drm/i915: Use IS_GEN in execbuffer Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 21/28] drm/i915: Allow render state to be compiled out Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 22/28] drm/i915: Use IS_GEN in stolen Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 23/28] drm/i915: Use IS_GEN in intel_bios.c Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 24/28] drm/i915: Use IS_GEN in intel_fb_pitch_limit Tvrtko Ursulin
2021-04-14 11:50 ` Tvrtko Ursulin [this message]
2021-04-14 11:50 ` [Intel-gfx] [RFC 26/28] drm/i915: Use IS_GEN in intel_guc.c Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 27/28] drm/i915: Use IS_GEN in intel_lrc.c Tvrtko Ursulin
2021-04-14 11:50 ` [Intel-gfx] [RFC 28/28] drm/i915: Enable dropping small cores when not enabled Tvrtko Ursulin
2021-04-14 12:25 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Old platform/gen kconfig options series Patchwork
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