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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 2/7] drm/i915/xelpd: Define plane capabilities
Date: Tue, 11 May 2021 21:21:39 -0700	[thread overview]
Message-ID: <20210512042144.2089071-3-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210512042144.2089071-1-matthew.d.roper@intel.com>

XE_LPD's plane support is identical to RKL and ADL-S --- 5 universal + 1
cursor with NV12 UV support on planes 1-3 and NV12 Y support on planes
4-5.

v2:
 - Drop the extra 90/270 rotation check in skl_plane_check_fb(); the DRM
   property code will already prevent userspace from passing us values
   that weren't advertised.  (Lucas)

Bspec: 53657
Bspec: 49251
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 11 +++++++----
 drivers/gpu/drm/i915/i915_irq.c                    |  2 +-
 drivers/gpu/drm/i915/intel_device_info.c           |  2 +-
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 8588b70a8241..d51a22d4b28a 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -268,7 +268,7 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 
 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
 {
-	if (HAS_D12_PLANE_MINIMIZATION(i915))
+	if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
 		return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
 	else
 		return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
@@ -2094,9 +2094,12 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 	if (ret)
 		goto fail;
 
-	supported_rotations =
-		DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
-		DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
+	if (DISPLAY_VER(dev_priv) >= 13)
+		supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
+	else
+		supported_rotations =
+			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
+			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
 
 	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
 		supported_rotations |= DRM_MODE_REFLECT_X;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 26a5474bb145..d4611c643446 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2309,7 +2309,7 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
 
 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
 {
-	if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
+	if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
 		return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
 	else if (DISPLAY_VER(dev_priv) >= 11)
 		return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 3b975ce1ff59..8cb58a238c68 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -268,7 +268,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 
-	if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
+	if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_sprites[pipe] = 4;
 	else if (INTEL_GEN(dev_priv) >= 11)
-- 
2.25.4

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  parent reply	other threads:[~2021-05-12  4:22 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-12  4:21 [Intel-gfx] [CI 0/7] CI pass for reviewed XeLPD / ADL-P patches Matt Roper
2021-05-12  4:21 ` [Intel-gfx] [CI 1/7] drm/i915/xelpd: Handle proper AUX interrupt bits Matt Roper
2021-05-12  4:21 ` Matt Roper [this message]
2021-05-12  4:21 ` [Intel-gfx] [CI 3/7] drm/i915/xelpd: Add XE_LPD power wells Matt Roper
2021-05-12  4:21 ` [Intel-gfx] [CI 4/7] drm/i915/xelpd: Required bandwidth increases when VT-d is active Matt Roper
2021-05-12  4:21 ` [Intel-gfx] [CI 5/7] drm/i915/xelpd: Add Wa_14011503030 Matt Roper
2021-05-12  4:21 ` [Intel-gfx] [CI 6/7] drm/i915/adl_p: Add PCH support Matt Roper
2021-05-12  4:21 ` [Intel-gfx] [CI 7/7] drm/i915/perf: Enable OA formats for ADL_P Matt Roper
2021-05-12  4:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for CI pass for reviewed XeLPD / ADL-P patches Patchwork
2021-05-12  5:10 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-05-12  5:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for CI pass for reviewed XeLPD / ADL-P patches (rev2) Patchwork
2021-05-12  6:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-05-12 16:18   ` Matt Roper
2021-05-12 16:43     ` Vudum, Lakshminarayana
2021-05-12 17:45     ` Vudum, Lakshminarayana
2021-05-12 17:23 ` Patchwork
2021-05-12 17:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-12 19:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for CI pass for reviewed XeLPD / ADL-P patches (rev3) Patchwork
2021-05-12 20:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-12 21:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for CI pass for reviewed XeLPD / ADL-P patches (rev2) Patchwork
2021-05-13  0:02   ` Matt Roper
2021-05-13  1:21 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for CI pass for reviewed XeLPD / ADL-P patches (rev3) Patchwork

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