Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
* [Intel-gfx] [PATCH 1/3] drm/i915/adlp: Require DPT FB CCS color planes to be 2MB aligned
@ 2021-05-24 17:27 Imre Deak
  2021-05-24 17:27 ` [Intel-gfx] [PATCH 2/3] drm/i915/adlp: Fix GEM VM asserts for DPT VMs Imre Deak
                   ` (4 more replies)
  0 siblings, 5 replies; 8+ messages in thread
From: Imre Deak @ 2021-05-24 17:27 UTC (permalink / raw)
  To: intel-gfx

All DPT FB color plane surface base addresses must be 2MB aligned. On
ADL_P this means that the offsets in CCS FB object must be also 2MB
aligned. Adjusting unaligned offsets for these FBs during commit time
(compensating with the x/y offsets) doesn't work, since the big
alignment would most probably lead to an x/y offset mismatch error
between the main and CCS planes.

We can overcome this limitation by remapping CCS FBs, so that each color
plane is at an aligned offset, leaving x/y for each plane unadjusted
during commit and so not causing an x/y mismatch error. However
remapping for CCS FBs will be done as a follow-up, so for now require
that user space allocates the FB obj with properly aligned planes.

v2: s/SZ_2M/512*4k/ for clarity. (Ville)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_fb.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index a005c68889e7c..c60a81a81c09c 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -355,8 +355,17 @@ static int intel_fb_offset_to_xy(int *x, int *y,
 	unsigned int height;
 	u32 alignment;
 
-	if (DISPLAY_VER(i915) >= 12 &&
-	    is_semiplanar_uv_plane(fb, color_plane))
+	/*
+	 * All DPT color planes must be 512*4k aligned (the amount mapped by a
+	 * single DPT page). For ADL_P CCS FBs this only works by requiring
+	 * the allocated offsets to be 2MB aligned.  Once supoort to remap
+	 * such FBs is added we can remove this requirement, as then all the
+	 * planes can be remapped to an aligned offset.
+	 */
+	if (IS_ALDERLAKE_P(i915) && is_ccs_modifier(fb->modifier))
+		alignment = 512 * 4096;
+	else if (DISPLAY_VER(i915) >= 12 &&
+		 is_semiplanar_uv_plane(fb, color_plane))
 		alignment = intel_tile_row_size(fb, color_plane);
 	else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
 		alignment = intel_tile_size(i915);
-- 
2.27.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2021-05-25  0:22 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-05-24 17:27 [Intel-gfx] [PATCH 1/3] drm/i915/adlp: Require DPT FB CCS color planes to be 2MB aligned Imre Deak
2021-05-24 17:27 ` [Intel-gfx] [PATCH 2/3] drm/i915/adlp: Fix GEM VM asserts for DPT VMs Imre Deak
2021-05-24 17:59   ` Souza, Jose
2021-05-24 17:27 ` [Intel-gfx] [PATCH 3/3] drm/i915/debugfs: Print remap info for DPT VMAs as well Imre Deak
2021-05-24 17:59   ` Souza, Jose
2021-05-24 18:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/adlp: Require DPT FB CCS color planes to be 2MB aligned Patchwork
2021-05-24 19:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-25  0:22 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox