From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 1/9] drm/i915/fbc: s/threshold/limit/
Date: Thu, 10 Jun 2021 21:32:29 +0300 [thread overview]
Message-ID: <20210610183237.3920-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210610183237.3920-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's call the compression limit the limit.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 50 ++++++++++++------------
drivers/gpu/drm/i915/i915_drv.h | 3 +-
2 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 1847a161cb37..715f5c60d9c5 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -104,7 +104,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
int i;
u32 fbc_ctl;
- /* Note: fbc.threshold == 1 for i8xx */
+ /* Note: fbc.limit == 1 for i8xx */
cfb_pitch = params->cfb_size / FBC_LL_SIZE;
if (params->fb.stride < cfb_pitch)
cfb_pitch = params->fb.stride;
@@ -235,13 +235,13 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
{
struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
u32 dpfc_ctl;
- int threshold = dev_priv->fbc.threshold;
+ int limit = dev_priv->fbc.limit;
dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
if (params->fb.format->cpp[0] == 2)
- threshold++;
+ limit++;
- switch (threshold) {
+ switch (limit) {
case 4:
case 3:
dpfc_ctl |= DPFC_CTL_LIMIT_4X;
@@ -300,7 +300,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
{
struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
u32 dpfc_ctl;
- int threshold = dev_priv->fbc.threshold;
+ int limit = dev_priv->fbc.limit;
/* Display WA #0529: skl, kbl, bxt. */
if (DISPLAY_VER(dev_priv) == 9) {
@@ -319,9 +319,9 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
if (params->fb.format->cpp[0] == 2)
- threshold++;
+ limit++;
- switch (threshold) {
+ switch (limit) {
case 4:
case 3:
dpfc_ctl |= DPFC_CTL_LIMIT_4X;
@@ -433,12 +433,12 @@ static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915)
return BIT_ULL(32);
}
-static int find_compression_threshold(struct drm_i915_private *dev_priv,
- struct drm_mm_node *node,
- unsigned int size,
- unsigned int fb_cpp)
+static int find_compression_limit(struct drm_i915_private *dev_priv,
+ struct drm_mm_node *node,
+ unsigned int size,
+ unsigned int fb_cpp)
{
- int compression_threshold = 1;
+ int compression_limit = 1;
int ret;
u64 end;
@@ -458,19 +458,19 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
* code changes, this code needs to change as well.
*
* The enable_fbc code will attempt to use one of our 2 compression
- * thresholds, therefore, in that case, we only have 1 resort.
+ * limits, therefore, in that case, we only have 1 resort.
*/
/* Try to over-allocate to reduce reallocations and fragmentation. */
ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
4096, 0, end);
if (ret == 0)
- return compression_threshold;
+ return compression_limit;
again:
/* HW's ability to limit the CFB is 1:4 */
- if (compression_threshold > 4 ||
- (fb_cpp == 2 && compression_threshold == 2))
+ if (compression_limit > 4 ||
+ (fb_cpp == 2 && compression_limit == 2))
return 0;
ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
@@ -478,10 +478,10 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
if (ret && DISPLAY_VER(dev_priv) <= 4) {
return 0;
} else if (ret) {
- compression_threshold <<= 1;
+ compression_limit <<= 1;
goto again;
} else {
- return compression_threshold;
+ return compression_limit;
}
}
@@ -495,8 +495,8 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
drm_WARN_ON(&dev_priv->drm,
drm_mm_node_allocated(&fbc->compressed_fb));
- ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
- size, fb_cpp);
+ ret = find_compression_limit(dev_priv, &fbc->compressed_fb,
+ size, fb_cpp);
if (!ret)
goto err_llb;
else if (ret > 1) {
@@ -504,7 +504,7 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
"Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
}
- fbc->threshold = ret;
+ fbc->limit = ret;
if (DISPLAY_VER(dev_priv) >= 5)
intel_de_write(dev_priv, ILK_DPFC_CB_BASE,
@@ -537,8 +537,8 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
}
drm_dbg_kms(&dev_priv->drm,
- "reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
- fbc->compressed_fb.size, fbc->threshold);
+ "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n",
+ fbc->compressed_fb.size, fbc->limit);
return 0;
@@ -753,7 +753,7 @@ static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
struct intel_fbc *fbc = &dev_priv->fbc;
return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
- fbc->compressed_fb.size * fbc->threshold;
+ fbc->compressed_fb.size * fbc->limit;
}
static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
@@ -763,7 +763,7 @@ static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
if ((DISPLAY_VER(dev_priv) == 9) &&
cache->fb.modifier != I915_FORMAT_MOD_X_TILED)
- return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;
+ return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->limit) * 8;
else
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 38ff2fb89744..5e482b8b8e94 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -346,7 +346,6 @@ struct intel_fbc {
/* This is always the inner lock when overlapping with struct_mutex and
* it's the outer lock when overlapping with stolen_lock. */
struct mutex lock;
- unsigned threshold;
unsigned int possible_framebuffer_bits;
unsigned int busy_bits;
struct intel_crtc *crtc;
@@ -354,6 +353,8 @@ struct intel_fbc {
struct drm_mm_node compressed_fb;
struct drm_mm_node *compressed_llb;
+ u8 limit;
+
bool false_color;
bool active;
--
2.31.1
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next prev parent reply other threads:[~2021-06-10 18:32 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-10 18:32 [Intel-gfx] [PATCH 0/9] drm/i915/fbc: Clean up cfb allocation code Ville Syrjala
2021-06-10 18:32 ` Ville Syrjala [this message]
2021-06-10 18:32 ` [Intel-gfx] [PATCH 2/9] drm/i915/fbc: Extract intel_fbc_program_cfb() Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 3/9] drm/i915/fbc: Embed the compressed_llb node Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 4/9] drm/i915/fbc: Don't pass around the mm node Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 5/9] drm/i915/fbc: Handle 16bpp compression limit better Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 6/9] drm/i915/fbc: Introduce g4x_dpfc_ctl_limit() Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 7/9] drm/i915/fbc: Extract intel_fbc_stolen_end() Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 8/9] drm/i915/fbc: Make the cfb allocation loop a bit more legible Ville Syrjala
2021-06-10 18:32 ` [Intel-gfx] [PATCH 9/9] drm/i915/fbc: Allocate llb before cfb Ville Syrjala
2021-06-18 21:07 ` Souza, Jose
2021-06-10 18:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Clean up cfb allocation code Patchwork
2021-06-10 19:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-10 22:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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