public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: matthew.auld@intel.com, Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH v3 06/12] drm/i915/gt: Export the pinned context constructor and destructor
Date: Mon, 14 Jun 2021 18:26:06 +0200	[thread overview]
Message-ID: <20210614162612.294869-7-thomas.hellstrom@linux.intel.com> (raw)
In-Reply-To: <20210614162612.294869-1-thomas.hellstrom@linux.intel.com>

From: Chris Wilson <chris@chris-wilson.co.uk>

Allow internal clients to create and destroy a pinned context.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
v2:
- (Thomas) Export also the pinned context destructor
---
 drivers/gpu/drm/i915/gt/intel_engine.h    | 11 +++++++++
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 ++++++++++++++---------
 2 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 8d9184920c51..36ea9eb52bb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -19,7 +19,9 @@
 #include "intel_workarounds.h"
 
 struct drm_printer;
+struct intel_context;
 struct intel_gt;
+struct lock_class_key;
 
 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
  * but keeps the logic simple. Indeed, the whole purpose of this macro is just
@@ -256,6 +258,15 @@ struct i915_request *
 intel_engine_find_active_request(struct intel_engine_cs *engine);
 
 u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
+struct intel_context *
+intel_engine_create_pinned_context(struct intel_engine_cs *engine,
+				   struct i915_address_space *vm,
+				   unsigned int ring_size,
+				   unsigned int hwsp,
+				   struct lock_class_key *key,
+				   const char *name);
+
+void intel_engine_destroy_pinned_context(struct intel_context *ce);
 
 void intel_engine_init_active(struct intel_engine_cs *engine,
 			      unsigned int subclass);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 9ceddfbb1687..fcbaad18ac91 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -810,11 +810,13 @@ intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
 #endif
 }
 
-static struct intel_context *
-create_pinned_context(struct intel_engine_cs *engine,
-		      unsigned int hwsp,
-		      struct lock_class_key *key,
-		      const char *name)
+struct intel_context *
+intel_engine_create_pinned_context(struct intel_engine_cs *engine,
+				   struct i915_address_space *vm,
+				   unsigned int ring_size,
+				   unsigned int hwsp,
+				   struct lock_class_key *key,
+				   const char *name)
 {
 	struct intel_context *ce;
 	int err;
@@ -825,6 +827,10 @@ create_pinned_context(struct intel_engine_cs *engine,
 
 	__set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
 	ce->timeline = page_pack_bits(NULL, hwsp);
+	ce->ring = __intel_context_ring_size(ring_size);
+
+	i915_vm_put(ce->vm);
+	ce->vm = i915_vm_get(vm);
 
 	err = intel_context_pin(ce); /* perma-pin so it is always available */
 	if (err) {
@@ -843,7 +849,7 @@ create_pinned_context(struct intel_engine_cs *engine,
 	return ce;
 }
 
-static void destroy_pinned_context(struct intel_context *ce)
+void intel_engine_destroy_pinned_context(struct intel_context *ce)
 {
 	struct intel_engine_cs *engine = ce->engine;
 	struct i915_vma *hwsp = engine->status_page.vma;
@@ -863,8 +869,9 @@ create_kernel_context(struct intel_engine_cs *engine)
 {
 	static struct lock_class_key kernel;
 
-	return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
-				     &kernel, "kernel_context");
+	return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,
+						  I915_GEM_HWS_SEQNO_ADDR,
+						  &kernel, "kernel_context");
 }
 
 /**
@@ -907,7 +914,7 @@ static int engine_init_common(struct intel_engine_cs *engine)
 	return 0;
 
 err_context:
-	destroy_pinned_context(ce);
+	intel_engine_destroy_pinned_context(ce);
 	return ret;
 }
 
@@ -969,7 +976,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 		fput(engine->default_state);
 
 	if (engine->kernel_context)
-		destroy_pinned_context(engine->kernel_context);
+		intel_engine_destroy_pinned_context(engine->kernel_context);
 
 	GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
 	cleanup_status_page(engine);
-- 
2.31.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2021-06-14 16:26 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-14 16:26 [Intel-gfx] [PATCH v3 00/12] i915 TTM sync accelerated migration and clear Thomas Hellström
2021-06-14 16:26 ` [Intel-gfx] [PATCH v3 01/12] drm/i915: Reference objects on the ww object list Thomas Hellström
2021-06-14 16:26 ` [Intel-gfx] [PATCH v3 02/12] drm/i915: Break out dma_resv ww locking utilities to separate files Thomas Hellström
2021-06-14 16:26 ` [Intel-gfx] [PATCH v3 03/12] drm/i915: Introduce a ww transaction helper Thomas Hellström
2021-06-14 16:26 ` [Intel-gfx] [PATCH v3 04/12] drm/i915/gt: Add an insert_entry for gen8_ppgtt Thomas Hellström
2021-06-14 16:26 ` [Intel-gfx] [PATCH v3 05/12] drm/i915/gt: Add a routine to iterate over the pagetables of a GTT Thomas Hellström
2021-06-14 16:26 ` Thomas Hellström [this message]
2021-06-14 16:26 ` [Intel-gfx] [PATCH v3 07/12] drm/i915/gt: Pipelined page migration Thomas Hellström
2021-06-15 14:45   ` Matthew Auld
2021-06-14 16:26 ` [Intel-gfx] [PATCH v3 08/12] drm/i915/gt: Pipelined clear Thomas Hellström
2021-06-15 14:47   ` Matthew Auld
2021-06-14 16:26 ` [Intel-gfx] [PATCH v3 09/12] drm/i915/gt: Setup a default migration context on the GT Thomas Hellström
2021-06-14 16:26 ` [Intel-gfx] [PATCH v3 10/12] drm/i915/ttm: accelerated move implementation Thomas Hellström
2021-06-14 17:55   ` Thomas Hellström
2021-06-15 10:06     ` [Intel-gfx] [PATCH v3] " Ramalingam C
2021-06-14 16:26 ` [Intel-gfx] [PATCH v3 11/12] drm/i915/gem: Zap the client blt code Thomas Hellström
2021-06-14 16:33   ` Matthew Auld
2021-06-14 16:40     ` Thomas Hellström
2021-06-14 16:26 ` [Intel-gfx] [PATCH v3 12/12] drm/i915/gem: Zap the i915_gem_object_blt code Thomas Hellström
2021-06-14 16:43   ` Matthew Auld
2021-06-15  0:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915 TTM sync accelerated migration and clear Patchwork
2021-06-15  1:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-15 10:19 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-06-15 11:45 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for i915 TTM sync accelerated migration and clear (rev2) Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210614162612.294869-7-thomas.hellstrom@linux.intel.com \
    --to=thomas.hellstrom@linux.intel.com \
    --cc=chris@chris-wilson.co.uk \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=matthew.auld@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox