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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 10/18] drm/i915/dg2: Add fake PCH
Date: Wed, 21 Jul 2021 15:30:35 -0700	[thread overview]
Message-ID: <20210721223043.834562-11-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210721223043.834562-1-matthew.d.roper@intel.com>

As with DG1, DG2 has an ICL-style south display interface provided on
the same PCI device.  Add a fake PCH to ensure DG2 takes the appropriate
codepaths for south display handling.

Bspec: 54871, 50062, 49961, 53673
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c  | 2 +-
 drivers/gpu/drm/i915/intel_pch.c | 3 +++
 drivers/gpu/drm/i915/intel_pch.h | 2 ++
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 61dceb2a17c1..e2171bd2820e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -207,7 +207,7 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 	    (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
 		return;
 
-	if (HAS_PCH_DG1(dev_priv))
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 		hpd->pch_hpd = hpd_sde_dg1;
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		hpd->pch_hpd = hpd_icp;
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 4e92ae19189e..cc44164e242b 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -211,6 +211,9 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
 	if (IS_DG1(dev_priv)) {
 		dev_priv->pch_type = PCH_DG1;
 		return;
+	} else if (IS_DG2(dev_priv)) {
+		dev_priv->pch_type = PCH_DG2;
+		return;
 	}
 
 	/*
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index e2f3f30c6445..7c0d83d292dc 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -30,6 +30,7 @@ enum intel_pch {
 
 	/* Fake PCHs, functionality handled on the same PCI dev */
 	PCH_DG1 = 1024,
+	PCH_DG2,
 };
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff80
@@ -62,6 +63,7 @@ enum intel_pch {
 
 #define INTEL_PCH_TYPE(dev_priv)		((dev_priv)->pch_type)
 #define INTEL_PCH_ID(dev_priv)			((dev_priv)->pch_id)
+#define HAS_PCH_DG2(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
 #define HAS_PCH_ADP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
 #define HAS_PCH_DG1(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
 #define HAS_PCH_JSP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
-- 
2.25.4

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  parent reply	other threads:[~2021-07-21 22:31 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-21 22:30 [Intel-gfx] [CI 00/18] CI pass for reviewed Xe_HP SDV and DG2 patches Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 01/18] drm/i915: Add XE_HP initial definitions Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 02/18] drm/i915/xehpsdv: add initial XeHP SDV definitions Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 03/18] drm/i915/dg2: add DG2 platform info Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 04/18] drm/i915: Fork DG1 interrupt handler Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 05/18] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 06/18] drm/i915/gen12: Use fuse info to enable SFC Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 07/18] drm/i915/selftests: Allow for larger engine counts Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 08/18] drm/i915/xehp: Handle new device context ID format Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 09/18] drm/i915/xehp: New engine context offsets Matt Roper
2021-07-21 22:30 ` Matt Roper [this message]
2021-07-21 22:30 ` [Intel-gfx] [CI 11/18] drm/i915/dg2: Add cdclk table and reference clock Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 12/18] drm/i915/dg2: Skip shared DPLL handling Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 13/18] drm/i915/dg2: Don't wait for AUX power well enable ACKs Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 14/18] drm/i915/dg2: Setup display outputs Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 15/18] drm/i915/dg2: Add dbuf programming Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 16/18] drm/i915/dg2: Don't program BW_BUDDY registers Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 17/18] drm/i915/dg2: Don't read DRAM info Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 18/18] drm/i915/dg2: DG2 has fixed memory bandwidth Matt Roper
2021-07-22  0:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for CI pass for reviewed Xe_HP SDV and DG2 patches Patchwork
2021-07-22  0:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-22  0:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-22  7:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-07-22 16:42   ` Matt Roper

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