From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 18/18] drm/i915/dg2: DG2 has fixed memory bandwidth
Date: Wed, 21 Jul 2021 15:30:43 -0700 [thread overview]
Message-ID: <20210721223043.834562-19-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210721223043.834562-1-matthew.d.roper@intel.com>
DG2 doesn't have a SAGV or QGV points that determine memory bandwidth.
Instead it has a constant amount of memory bandwidth available to
display that does not need to be reduced based on the number of active
planes.
For simplicity, we'll just modify driver initialization to create a
single dummy QGV point with the proper amount of memory bandwidth,
rather than trying to query the pcode for this information.
Bspec: 64631
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 0d5d52548925..f554c1974072 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -273,6 +273,26 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
return 0;
}
+static void dg2_get_bw_info(struct drm_i915_private *i915)
+{
+ struct intel_bw_info *bi = &i915->max_bw[0];
+
+ /*
+ * DG2 doesn't have SAGV or QGV points, just a constant max bandwidth
+ * that doesn't depend on the number of planes enabled. Create a
+ * single dummy QGV point to reflect that. DG2-G10 platforms have a
+ * constant 50 GB/s bandwidth, whereas DG2-G11 platforms have 38 GB/s.
+ */
+ bi->num_planes = 1;
+ bi->num_qgv_points = 1;
+ if (IS_DG2_G11(i915))
+ bi->deratedbw[0] = 38000;
+ else
+ bi->deratedbw[0] = 50000;
+
+ i915->sagv_status = I915_SAGV_NOT_CONTROLLED;
+}
+
static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
int num_planes, int qgv_point)
{
@@ -306,7 +326,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
+ if (IS_DG2(dev_priv))
+ dg2_get_bw_info(dev_priv);
+ else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
icl_get_bw_info(dev_priv, &adls_sa_info);
else if (IS_ROCKETLAKE(dev_priv))
icl_get_bw_info(dev_priv, &rkl_sa_info);
--
2.25.4
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next prev parent reply other threads:[~2021-07-21 22:31 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-21 22:30 [Intel-gfx] [CI 00/18] CI pass for reviewed Xe_HP SDV and DG2 patches Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 01/18] drm/i915: Add XE_HP initial definitions Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 02/18] drm/i915/xehpsdv: add initial XeHP SDV definitions Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 03/18] drm/i915/dg2: add DG2 platform info Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 04/18] drm/i915: Fork DG1 interrupt handler Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 05/18] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 06/18] drm/i915/gen12: Use fuse info to enable SFC Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 07/18] drm/i915/selftests: Allow for larger engine counts Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 08/18] drm/i915/xehp: Handle new device context ID format Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 09/18] drm/i915/xehp: New engine context offsets Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 10/18] drm/i915/dg2: Add fake PCH Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 11/18] drm/i915/dg2: Add cdclk table and reference clock Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 12/18] drm/i915/dg2: Skip shared DPLL handling Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 13/18] drm/i915/dg2: Don't wait for AUX power well enable ACKs Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 14/18] drm/i915/dg2: Setup display outputs Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 15/18] drm/i915/dg2: Add dbuf programming Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 16/18] drm/i915/dg2: Don't program BW_BUDDY registers Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 17/18] drm/i915/dg2: Don't read DRAM info Matt Roper
2021-07-21 22:30 ` Matt Roper [this message]
2021-07-22 0:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for CI pass for reviewed Xe_HP SDV and DG2 patches Patchwork
2021-07-22 0:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-22 0:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-22 7:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-07-22 16:42 ` Matt Roper
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