From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: "José Roberto de Souza" <jose.souza@intel.com>,
"Jani Nikula" <jani.nikula@intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>
Subject: [Intel-gfx] [PATCH 0/6] drm/i915/dp: Fix link parameter use in lack of a valid DPCD
Date: Mon, 18 Oct 2021 12:41:48 +0300 [thread overview]
Message-ID: <20211018094154.1407705-1-imre.deak@intel.com> (raw)
This patchset fixes a few issues, related to invalid accesses from the
intel_dp->common_rates[] array and in general the link rate, lane count
parameters being invalid until a valid DPCD is read from the sink.
One issue in intel_dp_sync_state() was caught by the CONFIG_UBSAN
feature. The first 3 patches are also needed for stable kernels.
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Imre Deak (6):
drm/i915/dp: Skip the HW readout of DPCD on disabled encoders
drm/i915/dp: Ensure sink rate values are always valid
drm/i915/dp: Ensure max link params are always valid
drm/i915/dp: Ensure sink/link max lane count values are always valid
drm/i915/dp: Sanitize sink rate DPCD register values
drm/i915/dp: Sanitize link common rate array lookups
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 127 ++++++++++++++----
2 files changed, 101 insertions(+), 28 deletions(-)
--
2.27.0
next reply other threads:[~2021-10-18 9:42 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-18 9:41 Imre Deak [this message]
2021-10-18 9:41 ` [Intel-gfx] [PATCH 1/6] drm/i915/dp: Skip the HW readout of DPCD on disabled encoders Imre Deak
2021-10-18 9:41 ` [Intel-gfx] [PATCH 2/6] drm/i915/dp: Ensure sink rate values are always valid Imre Deak
2021-10-18 14:34 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-19 7:27 ` [Intel-gfx] [PATCH " Jani Nikula
2021-10-19 7:33 ` Imre Deak
2021-10-19 7:37 ` Jani Nikula
2021-10-19 7:39 ` Imre Deak
2021-10-19 18:37 ` Imre Deak
2021-10-19 19:17 ` Jani Nikula
2021-10-18 9:41 ` [Intel-gfx] [PATCH 3/6] drm/i915/dp: Ensure max link params " Imre Deak
2021-10-18 9:41 ` [Intel-gfx] [PATCH 4/6] drm/i915/dp: Ensure sink/link max lane count values " Imre Deak
2021-10-18 15:04 ` Ville Syrjälä
2021-10-18 15:13 ` Imre Deak
2021-10-18 15:27 ` Ville Syrjälä
2021-10-18 9:41 ` [Intel-gfx] [PATCH 5/6] drm/i915/dp: Sanitize sink rate DPCD register values Imre Deak
2021-10-18 9:41 ` [Intel-gfx] [PATCH 6/6] drm/i915/dp: Sanitize link common rate array lookups Imre Deak
2021-10-19 19:23 ` Jani Nikula
2021-10-20 9:06 ` Imre Deak
2021-10-20 9:53 ` Jani Nikula
2021-10-20 10:09 ` Ville Syrjälä
2021-10-18 12:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Fix link parameter use in lack of a valid DPCD Patchwork
2021-10-18 12:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-18 13:06 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-10-18 18:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2) Patchwork
2021-10-18 18:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-18 18:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-19 0:52 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-19 12:54 ` Imre Deak
2021-10-19 15:33 ` Vudum, Lakshminarayana
2021-10-19 16:32 ` Imre Deak
2021-10-19 14:45 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2021-10-20 15:40 ` Imre Deak
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