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* [Intel-gfx] [PATCH v2 1/4] drm/i915/clflush: fixup handling of cache_dirty
@ 2021-10-27 16:18 Matthew Auld
  2021-10-27 16:18 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/clflush: disallow on discrete Matthew Auld
                   ` (11 more replies)
  0 siblings, 12 replies; 15+ messages in thread
From: Matthew Auld @ 2021-10-27 16:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel, Thomas Hellström

In theory if clflush_work_create() somehow fails here, and we don't yet
have mm.pages populated then we end up resetting cache_dirty, which is
likely wrong, since that will potentially skip the flush-on-acquire, if
it was needed.

It looks like intel_user_framebuffer_dirty() can arrive here before the
pages are populated.

v2(Thomas):
  - Move setting cache_dirty out of the async portion, also add a
    comment for why that should still be safe.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
index f0435c6feb68..47586a8a1b73 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
@@ -109,12 +109,20 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
 						I915_FENCE_GFP);
 		dma_resv_add_excl_fence(obj->base.resv, &clflush->base.dma);
 		dma_fence_work_commit(&clflush->base);
+		/*
+		 * We must have successfully populated the pages(since we are
+		 * holding a pin on the pages as per the flush worker) to reach
+		 * this point, which must mean we have already done the required
+		 * flush-on-acquire, hence resetting cache_dirty here should be
+		 * safe.
+		 */
+		obj->cache_dirty = false;
 	} else if (obj->mm.pages) {
 		__do_clflush(obj);
+		obj->cache_dirty = false;
 	} else {
 		GEM_BUG_ON(obj->write_domain != I915_GEM_DOMAIN_CPU);
 	}
 
-	obj->cache_dirty = false;
 	return true;
 }
-- 
2.26.3


^ permalink raw reply related	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2021-10-29 16:11 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-10-27 16:18 [Intel-gfx] [PATCH v2 1/4] drm/i915/clflush: fixup handling of cache_dirty Matthew Auld
2021-10-27 16:18 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/clflush: disallow on discrete Matthew Auld
2021-10-27 16:18 ` [Intel-gfx] [PATCH v2 3/4] drm/i915: move cpu_write_needs_clflush Matthew Auld
2021-10-27 16:18 ` [Intel-gfx] [PATCH v2 4/4] drm/i915: stop setting cache_dirty on discrete Matthew Auld
2021-10-27 18:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/4] drm/i915/clflush: fixup handling of cache_dirty Patchwork
2021-10-27 18:12 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-27 18:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-28  0:59 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-28  8:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/4] drm/i915/clflush: fixup handling of cache_dirty (rev2) Patchwork
2021-10-28  8:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-28  9:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-28 12:57 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-29  9:10   ` Matthew Auld
2021-10-29 16:06     ` Vudum, Lakshminarayana
2021-10-29 15:36 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork

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