From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: michael.cheng@intel.com, wayne.boyer@intel.com,
jani.nikula@intel.com, lucas.demarchi@intel.com,
siva.mullati@intel.com
Subject: [Intel-gfx] [PATCH 0/1] Introduce new i915 macros for checking PTEs
Date: Mon, 8 Nov 2021 10:04:38 -0800 [thread overview]
Message-ID: <20211108180439.848904-1-michael.cheng@intel.com> (raw)
This series is to introduce new macros generic to i915 for checking 0 and 1 bits,
instead on relying on whats defined by the mmu, since it could be different
or non-exisitent between different platforms.
Michael Cheng (1):
drm/i915: Introduce new macros for i915 PTE
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++
drivers/gpu/drm/i915/gvt/gtt.c | 12 ++++++------
4 files changed, 13 insertions(+), 10 deletions(-)
--
2.25.1
next reply other threads:[~2021-11-08 18:05 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-08 18:04 Michael Cheng [this message]
2021-11-08 18:04 ` [Intel-gfx] [PATCH 1/1] drm/i915: Introduce new macros for i915 PTE Michael Cheng
2021-11-08 19:04 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce new i915 macros for checking PTEs Patchwork
2021-11-08 19:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-11-08 21:26 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2021-11-08 17:19 [Intel-gfx] [PATCH 0/1] " Michael Cheng
2021-11-08 17:40 ` Jani Nikula
2021-11-08 20:21 ` Slade Watkins
2021-11-08 21:39 ` Lucas De Marchi
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