[Intel-gfx] [PATCH v3 0/8] DG2 accelerated migration/clearing support

[Matthew Auld <matthew.auld@intel.com>]

Enable accelerated moves and clearing on DG2. On such HW we have minimum page
size restrictions when accessing LMEM from the GTT, where we now have to use 64K
GTT pages or larger. With the ppGTT the page-table also has a slightly different
layout from past generations when using the 64K GTT mode(which is still enabled
on via some PDE bit), where it is now compacted down to 32 qword entries. Note
that on discrete the paging structures must also be placed in LMEM, and we need
to able to modify them via the GTT itself(see patch 7), which is one of the
complications here.

The series needs to be applied on top of the DG2 enabling branch:
https://cgit.freedesktop.org/~ramaling/linux/log/?h=dg2_enabling_ww49.3

Matthew Auld (8):
  drm/i915/migrate: don't check the scratch page
  drm/i915/migrate: fix offset calculation
  drm/i915/migrate: fix length calculation
  drm/i915/selftests: handle object rounding
  drm/i915/gtt: allow overriding the pt alignment
  drm/i915/gtt: add xehpsdv_ppgtt_insert_entry
  drm/i915/migrate: add acceleration support for DG2
  drm/i915/migrate: turn on acceleration for DG2

 drivers/gpu/drm/i915/gt/gen8_ppgtt.c       |  50 +++++-
 drivers/gpu/drm/i915/gt/intel_gtt.h        |  10 +-
 drivers/gpu/drm/i915/gt/intel_migrate.c    | 195 ++++++++++++++++-----
 drivers/gpu/drm/i915/gt/intel_ppgtt.c      |  16 +-
 drivers/gpu/drm/i915/gt/selftest_migrate.c |   1 +
 5 files changed, 221 insertions(+), 51 deletions(-)

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2.31.1