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From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: michael.cheng@intel.com, lucas.demarchi@intel.com,
	dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v11 5/6] drm/i915/: Re-work clflush_write32
Date: Tue, 22 Feb 2022 21:58:59 -0800	[thread overview]
Message-ID: <20220223055900.415627-6-michael.cheng@intel.com> (raw)
In-Reply-To: <20220223055900.415627-1-michael.cheng@intel.com>

Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.

v2(Michael Cheng): Use sizeof(*addr) instead of sizeof(addr) to get the
		   actual size of the page. Thanks to Matt Roper for
		   pointing this out.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 89aa0557ade1..0ca6c3d810da 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1333,10 +1333,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 {
 	if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
-		if (flushes & CLFLUSH_BEFORE) {
-			clflushopt(addr);
-			mb();
-		}
+		if (flushes & CLFLUSH_BEFORE)
+			drm_clflush_virt_range(addr, sizeof(*addr));
 
 		*addr = value;
 
@@ -1348,7 +1346,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 		 * to ensure ordering of clflush wrt to the system.
 		 */
 		if (flushes & CLFLUSH_AFTER)
-			clflushopt(addr);
+			drm_clflush_virt_range(addr, sizeof(*addr));
 	} else
 		*addr = value;
 }
-- 
2.25.1


  parent reply	other threads:[~2022-02-23  5:59 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-23  5:58 [Intel-gfx] [PATCH v11 0/6] Use drm_clflush* instead of clflush Michael Cheng
2022-02-23  5:58 ` [Intel-gfx] [PATCH v11 1/6] drm: Add arch arm64 for drm_clflush_virt_range Michael Cheng
2022-02-23  9:56   ` kernel test robot
2022-02-23 12:46   ` kernel test robot
2022-02-23 17:43   ` kernel test robot
2022-02-23  5:58 ` [Intel-gfx] [PATCH v11 2/6] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-02-23  5:58 ` [Intel-gfx] [PATCH v11 3/6] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
2022-02-23  5:58 ` [Intel-gfx] [PATCH v11 4/6] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-02-23  5:58 ` Michael Cheng [this message]
2022-02-23  5:59 ` [Intel-gfx] [PATCH v11 6/6] drm/i915/gt: replace cache_clflush_range Michael Cheng
2022-02-23  8:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev10) Patchwork
2022-02-23  8:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-23  8:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-24  4:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev11) Patchwork
2022-02-24  4:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-24  4:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-24 16:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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