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From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: michael.cheng@intel.com, lucas.demarchi@intel.com,
	dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v12 5/6] drm/i915/: Re-work clflush_write32
Date: Thu, 24 Feb 2022 19:24:35 -0800	[thread overview]
Message-ID: <20220225032436.904942-6-michael.cheng@intel.com> (raw)
In-Reply-To: <20220225032436.904942-1-michael.cheng@intel.com>

Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.

v2(Michael Cheng): Use sizeof(*addr) instead of sizeof(addr) to get the
		   actual size of the page. Thanks to Matt Roper for
		   pointing this out.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 89aa0557ade1..0ca6c3d810da 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1333,10 +1333,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 {
 	if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
-		if (flushes & CLFLUSH_BEFORE) {
-			clflushopt(addr);
-			mb();
-		}
+		if (flushes & CLFLUSH_BEFORE)
+			drm_clflush_virt_range(addr, sizeof(*addr));
 
 		*addr = value;
 
@@ -1348,7 +1346,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 		 * to ensure ordering of clflush wrt to the system.
 		 */
 		if (flushes & CLFLUSH_AFTER)
-			clflushopt(addr);
+			drm_clflush_virt_range(addr, sizeof(*addr));
 	} else
 		*addr = value;
 }
-- 
2.25.1


  parent reply	other threads:[~2022-02-25  3:25 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-25  3:24 [Intel-gfx] [PATCH v12 0/6] Use drm_clflush* instead of clflush Michael Cheng
2022-02-25  3:24 ` [Intel-gfx] [PATCH v12 1/6] drm: Add arch arm64 for drm_clflush_virt_range Michael Cheng
2022-02-25 16:28   ` Tvrtko Ursulin
2022-02-25 16:52     ` Michael Cheng
2022-02-25 17:33       ` Tvrtko Ursulin
2022-02-25 17:40         ` Michael Cheng
2022-02-25 18:19           ` Tvrtko Ursulin
2022-02-25 18:23             ` Michael Cheng
2022-02-25 18:42               ` Tvrtko Ursulin
2022-02-25 18:58                 ` Matthew Wilcox
2022-02-25 18:24   ` Robin Murphy
2022-02-25 19:27     ` Michael Cheng
2022-03-02 12:49       ` Robin Murphy
2022-03-02 15:55         ` Michael Cheng
2022-03-02 17:06           ` Alex Deucher
2022-03-02 19:10           ` Robin Murphy
2022-03-07 16:52             ` Michael Cheng
2022-02-25  3:24 ` [Intel-gfx] [PATCH v12 2/6] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-02-25  3:24 ` [Intel-gfx] [PATCH v12 3/6] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
2022-02-25  3:24 ` [Intel-gfx] [PATCH v12 4/6] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-02-25  3:24 ` Michael Cheng [this message]
2022-02-25  3:24 ` [Intel-gfx] [PATCH v12 6/6] drm/i915/gt: replace cache_clflush_range Michael Cheng
2022-02-25  7:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush Patchwork
2022-02-25  7:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-25  7:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-26  1:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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